SNLA132G October 2011 – November 2020 DS90UB928Q-Q1 , DS90UB941AS-Q1 , DS90UB948-Q1 , DS90UH925Q-Q1 , DS90UH926Q-Q1 , DS90UH940N-Q1
The Internal Test Pattern generator is configured and enabled from the internal control registers, accessible locally through the I2C control interface, or remotely via the FPD-Link III Bidirectional Control Channel. The Pattern Generator control registers consist of both a Direct Register Map, as well as an Indirect Register Map, the latter of which is accessible through an indirect address pointer/data mechanism.