SNLA132G October   2011  – November 2020 DS90UB928Q-Q1 , DS90UB941AS-Q1 , DS90UB948-Q1 , DS90UH925Q-Q1 , DS90UH926Q-Q1 , DS90UH940N-Q1

 

  1.   Trademarks
  2. 1Introduction
  3. 2Overview of Internal Test Pattern Generation
    1. 2.1 Color Mode
    2. 2.2 Video Timing Modes
    3. 2.3 Clock Generation
    4. 2.4 Pattern Selection
    5. 2.5 Pattern Inversion
    6. 2.6 Auto-Scrolling
  4. 3Serial Control Bus Registers for Internal Test Pattern Generation
    1. 3.1 Direct Register Map
      1. 3.1.1 Control and Configuration
      2. 3.1.2 Indirect Access Address and Data
      3. 3.1.3 DS90Ux928Q-Q1/DS90UB924-Q1 Internal Clock Source
    2. 3.2 Indirect Register Map
      1. 3.2.1 General Control
      2. 3.2.2 Internal Timing Control
      3. 3.2.3 Auto-Scrolling Control
  5. 4Configuration Examples
    1. 4.1 Auto-Scrolling Configuration
    2. 4.2 Internal Default Timing Configuration
    3. 4.3 Custom Display Configuration
    4. 4.4 1080p60 with External Clock Example Configuration
    5. 4.5 Resolution Readback Example
  6. 5Conclusion
  7. 6References
  8. 7Revision History

3.2.3 Auto-Scrolling Control

Pattern Generator Frame Time (PGFT), Offset 0x0F in Table 3-4.

This register configures the number of frames to display each pattern when Auto-Scrolling is enabled.

Table 3-21 Pattern Generator Frame Time (PGFT)
BitAccessFieldDefault (bin)Description
7:0RWPATGEN_FTIME00011110Frame Time:
When Auto-Scrolling is enabled, this field controls the number of frames to display each pattern, in increments of two frames. Valid register values are 1-255, giving a programmable range of the even numbers between 2 and 510, inclusive.

Pattern Generator Time Slot Configuration (PGTSC), Offset 0X10 in Table 3-4.

This register configures the number of time slots enabled for Auto-Scrolling.

Table 3-22 Pattern Generator Time Slot Configuration (PGTSC)
BitAccessFieldDefault (bin)Description
7:4Reserved0000Reserved:
Reads return 0, writes are ignored.
3:0RWPATGEN_TSLOT1110Time Slots:
This field configures the number of enabled time slots for Auto-Scrolling. Valid values are 1-14 (925Q/921/926Q) or 1-16 (All other aforementioned devices).

Pattern Generator Time Slot Order 1 (PGTSO1), Offset 0X11 in Table 3-4.

This register configures patterns for Time Slots 1 and 2.

Table 3-23 Pattern Generator Time Slot Order 1 (PGTSO1)
BitAccessFieldDefault (bin)Description
7:4RWPATGEN_TS20010Time Slot 2 Pattern:
This field configures the pattern enabled in Time Slot 2. Valid values are 1-14 (925Q/921/926Q) or 0-15 (All other aforementioned devices).
3:0RWPATGEN_TS10001Time Slot 1 Pattern:
This field configures the pattern enabled in Time Slot 1. Valid values are 1-14 (925Q/921/926Q) or 0-15 (All other aforementioned devices).

Pattern Generator Time Slot Order 2 (PGTSO2), Offset 0X12 in Table 3-4.

This register configures patterns for Time Slots 3 and 4.

Table 3-24 Pattern Generator Time Slot Order 2 (PGTSO2)
BitAccessFieldDefault (bin)Description
7:4RWPATGEN_TS40100Time Slot 4 Pattern:
This field configures the pattern enabled in Time Slot 4. Valid values are 1-14 (925Q/921/926Q) or 0-15 (All other aforementioned devices).
3:0RWPATGEN_TS30011Time Slot 3 Pattern:
This field configures the pattern enabled in Time Slot 3. Valid values are 1-14 (925Q/921/926Q) or 0-15 (All other aforementioned devices).

Pattern Generator Time Slot Order 3 (PGTSO3), Offset 0X13 in Table 3-4.

This register configures patterns for Time Slots 5 and 6.

Table 3-25 Pattern Generator Time Slot Order 3 (PGTSO3)
BitAccessFieldDefault (bin)Description
7:4RWPATGEN_TS60110Time Slot 6 Pattern:
This field configures the pattern enabled in Time Slot 6. Valid values are 1-14 (925Q/921/926Q) or 0-15 (All other aforementioned devices).
3:0RWPATGEN_TS50101Time Slot 5 Pattern:
This field configures the pattern enabled in Time Slot 5. Valid values are 1-14 (925Q/921/926Q) or 0-15 (All other aforementioned devices).

Pattern Generator Time Slot Order 4 (PGTSO4), Offset 0X14 in Table 3-4.

This register configures patterns for Time Slots 7 and 8.

Table 3-26 Pattern Generator Time Slot Order 4 (PGTSO4)
BitAccessFieldDefault (bin)Description
7:4RWPATGEN_TS81000Time Slot 8 Pattern:
This field configures the pattern enabled in Time Slot 8. Valid values are 1-14 (925Q/921/926Q) or 0-15 (All other aforementioned devices).
3:0RWPATGEN_TS70111Time Slot 7 Pattern:
This field configures the pattern enabled in Time Slot 7. Valid values are 1-14 (925Q/921/926Q) or 0-15 (All other aforementioned devices).

Pattern Generator Time Slot Order 5 (PGTSO5), Offset 0X15 in Table 3-4.

This register configures patterns for Time Slots 9 and 10.

Table 3-27 Pattern Generator Time Slot Order 5 (PGTSO5)
BitAccessFieldDefault (bin)Description
7:4RWPATGEN_TS101010Time Slot 10 Pattern:
This field configures the pattern enabled in Time Slot 10. Valid values are 1-14 (925Q/921/926Q) or 0-15 (All other aforementioned devices).
3:0RWPATGEN_TS91001Time Slot 9 Pattern:
This field configures the pattern enabled in Time Slot 9. Valid values are 1-14 (925Q/921/926Q) or 0-15 (All other aforementioned devices).

Pattern Generator Time Slot Order 6 (PGTSO6), Offset 0X16 in Table 3-4.

This register configures patterns for Time Slots 11 and 12.

Table 3-28 Pattern Generator Time Slot Order 6 (PGTSO6)
BitAccessFieldDefault (bin)Description
7:4RWPATGEN_TS121100Time Slot 12 Pattern:
This field configures the pattern enabled in Time Slot 12. Valid values are 1-14 (925Q/921/926Q) or 0-15 (All other aforementioned devices).
3:0RWPATGEN_TS111011Time Slot 11 Pattern:
This field configures the pattern enabled in Time Slot 11. Valid values are 1-14 (925Q/921/926Q) or 0-15 (All other aforementioned devices).

Pattern Generator Time Slot Order 7 (PGTSO7), Offset 0X17 in Table 3-4.

This register configures patterns for Time Slots 13 and 14.

Table 3-29 Pattern Generator Time Slot Order 7 (PGTSO7)
BitAccessFieldDefault (bin)Description
7:4RWPATGEN_TS141110Time Slot 14 Pattern:
This field configures the pattern enabled in Time Slot 14. Valid values are 1-14 (925Q/921/926Q) or 0-15 (All other aforementioned devices).
3:0RWPATGEN_TS131101Time Slot 13 Pattern:
This field configures the pattern enabled in Time Slot 13. Valid values are 1-14 (925Q/921/926Q) or 0-15 (All other aforementioned devices).

Pattern Generator Time Slot Order 8 (PGTSO8), Offset 0X18 in Table 3-4.

This register configures patterns for Time Slots 15 and 16.

Table 3-30 Pattern Generator Time Slot Order 8 (PGTSO8, Not available on 925Q/921/926Q)
BitAccessFieldDefault (bin)Description
7:4RWPATGEN_TS160000Time Slot 16 Pattern:
This field configures the pattern enabled in Time Slot 16. Valid values are 0-15.
3:0RWPATGEN_TS151111Time Slot 15 Pattern:
This field configures the pattern enabled in Time Slot 15. Valid values are 0-15.

Pattern Generator BIST Errors (PGBE, Only Available on DS90Ux948-Q1 and DS90Ux940-Q1/DS90Ux940N-Q1), Offset 0X19 in Table 3-4.

This register is used for reading back error counts from PATGEN BIST (Built in Self Test).

Table 3-31 Pattern Generator BIST Errors (PGBE, Only Available on DS90Ux948-Q1 and DS90Ux940-Q1/DS90Ux940N-Q1)
BitAccessFieldDefault (bin)Description
7:0RPATGEN_BIST_ERRS00000000PATGEN BIST error count - Clear on read

Pattern Generator Clock Divider M Configuration (PGCDC2, Only Available on DS90Ux941AS-Q1, DS90Ux949-Q1, DS90Ux949A-Q1, DS90Ux929-Q1, and DS90Ux947-Q1), Offset 0X1A in Table 3-4.

This register configures the M divider value for the 941AS/949/949A/929/947 device. Adjusting this value can enable usage of the 800MHz nominal clock instead of the 200MHz nominal clock. When using 800MHz clock PATGEN, it is recommended to force the FPD-Link single/dual mode to prevent the device from falsely detecting the single/dual operational mode. See the DUAL_CTL1 register in the corresponding serializer for settings to force either single or dual FPD-Link.

Table 3-32 Pattern Generator Clock Divider M Configuration (PGCDC2, Only Available on DS90Ux941AS-Q1, DS90Ux949-Q1, DS90Ux949A-Q1, DS90Ux929-Q1, and DS90Ux947-Q1)
BitAccessFieldDefault (bin)Description
7:5RRESERVED0000
4:0RWPATGEN_CDIV_M0001Clock Divider: This field configures the "M" clock divider for the internally generated pixel clock on the 941AS/949/949A/929/947. If PGCDC2:PGEN_CDIV_M is 1, the internal pixel clock frequency is nominally (200/N) MHz. If PGCDC2:PGEN_CDIV_M is greater than 1, the internal pixel clock frequency is nominally (800*M/N) MHz.