SNLA132G October   2011  – November 2020 DS90UB928Q-Q1 , DS90UB941AS-Q1 , DS90UB948-Q1 , DS90UH925Q-Q1 , DS90UH926Q-Q1 , DS90UH940N-Q1

 

  1.   Trademarks
  2. 1Introduction
  3. 2Overview of Internal Test Pattern Generation
    1. 2.1 Color Mode
    2. 2.2 Video Timing Modes
    3. 2.3 Clock Generation
    4. 2.4 Pattern Selection
    5. 2.5 Pattern Inversion
    6. 2.6 Auto-Scrolling
  4. 3Serial Control Bus Registers for Internal Test Pattern Generation
    1. 3.1 Direct Register Map
      1. 3.1.1 Control and Configuration
      2. 3.1.2 Indirect Access Address and Data
      3. 3.1.3 DS90Ux928Q-Q1/DS90UB924-Q1 Internal Clock Source
    2. 3.2 Indirect Register Map
      1. 3.2.1 General Control
      2. 3.2.2 Internal Timing Control
      3. 3.2.3 Auto-Scrolling Control
  5. 4Configuration Examples
    1. 4.1 Auto-Scrolling Configuration
    2. 4.2 Internal Default Timing Configuration
    3. 4.3 Custom Display Configuration
    4. 4.4 1080p60 with External Clock Example Configuration
    5. 4.5 Resolution Readback Example
  6. 5Conclusion
  7. 6References
  8. 7Revision History

2.2 Video Timing Modes

The pattern generator offers two video timing modes: external and internal. In external timing mode (default), the pattern generator detects the video frame timing present on the DE and VS inputs. If Vertical Sync signaling is not present on VS, the pattern generator determines Vertical Blank by detecting when the number of inactive pixel clocks (DE = 0) exceeds twice the detected active line length. In internal timing mode, the pattern generator generates custom video timing as determined by the control registers.