SNLA132G October   2011  – November 2020 DS90UB928Q-Q1 , DS90UB941AS-Q1 , DS90UB948-Q1 , DS90UH925Q-Q1 , DS90UH926Q-Q1 , DS90UH940N-Q1

 

  1.   Trademarks
  2. 1Introduction
  3. 2Overview of Internal Test Pattern Generation
    1. 2.1 Color Mode
    2. 2.2 Video Timing Modes
    3. 2.3 Clock Generation
    4. 2.4 Pattern Selection
    5. 2.5 Pattern Inversion
    6. 2.6 Auto-Scrolling
  4. 3Serial Control Bus Registers for Internal Test Pattern Generation
    1. 3.1 Direct Register Map
      1. 3.1.1 Control and Configuration
      2. 3.1.2 Indirect Access Address and Data
      3. 3.1.3 DS90Ux928Q-Q1/DS90UB924-Q1 Internal Clock Source
    2. 3.2 Indirect Register Map
      1. 3.2.1 General Control
      2. 3.2.2 Internal Timing Control
      3. 3.2.3 Auto-Scrolling Control
  5. 4Configuration Examples
    1. 4.1 Auto-Scrolling Configuration
    2. 4.2 Internal Default Timing Configuration
    3. 4.3 Custom Display Configuration
    4. 4.4 1080p60 with External Clock Example Configuration
    5. 4.5 Resolution Readback Example
  6. 5Conclusion
  7. 6References
  8. 7Revision History

3.1.3 DS90Ux928Q-Q1/DS90UB924-Q1 Internal Clock Source

The DS90Ux928Q-Q1 and DS90UB924-Q1 deserializers require an extra configuration step to use their internal clock source. Note that this step is unnecessary if the pixel clock is derived externally (that is received from the serializer). Before enabling the Internal Test Pattern Generator with an internal pixel clock source, configure the register shown below:

Table 3-3 DS90Ux928Q-Q1/DS90UB924-Q1 Pattern Generator Internal Clock Enable
ADD(hex) Register Name Bit Access Default (hex) Function Description
0x39 PG Internal Clock Enable 7:2 0x00 Reserved
1 RW PG INT CLK Enable Pattern Generator Internal Clock
This bit must be used to set the Pattern Generator Internal Clock Generation
0: Pattern Generator with external PCLK
1: Pattern Generator with internal PCLK
0 Reserved