SNLA266A January   2016  – December 2023 DP83822H , DP83822HF , DP83822I , DP83822IF , DP83825I , DP83826E , DP83826I

 

  1.   1
  2.   DP8382x IEEE 802.3u Compliance and Debug
  3.   Trademarks
  4. 1Terminology
  5. 2Standards and System Requirements
    1. 2.1 Standards
    2. 2.2 Test Equipment Suppliers
    3. 2.3 Test Equipment Requirements
  6. 3Ethernet Physical Layer Compliance Testing
    1. 3.1 Standard Test Setup and Procedures
    2. 3.2 100BASE-TX Compliance Testing
      1. 3.2.1 Template (Active Output Interface)
      2. 3.2.2 Differential Output Voltage
      3. 3.2.3 Rise and Fall Time
      4. 3.2.4 Waveform Overshoot
      5. 3.2.5 Jitter
      6. 3.2.6 Duty Cycle Distortion
      7. 3.2.7 Return Loss
    3. 3.3 10BASE-Te Compliance Testing
      1. 3.3.1 Link Pulse
      2. 3.3.2 10BASE-Te Standard
        1. 3.3.2.1 TP_IDL
        2. 3.3.2.2 MAU, Internal
        3. 3.3.2.3 Jitter With TPM
        4. 3.3.2.4 Jitter Without TPM
        5. 3.3.2.5 Differential Voltage
        6. 3.3.2.6 Common-Mode Voltage
        7. 3.3.2.7 Return Loss
        8. 3.3.2.8 Harmonic Content
  7. 4How to Tune DP83825 VoD Swing
    1. 4.1 Example of Tuning DP83825 VoD Swing
  8. 5IEEE802.3u Compliance Testing Scripts for the DP8382x
  9. 6References
  10. 7Revision History

3.3.1 Link Pulse

Purpose: To verify that the link pulse waveform is within the specified bounds.

Pass Condition: The link pulse must fit into the IEEE-defined template in IEEE802.3-2005 Sub Clause 14.3.1.

Specific Test Setup: Verify the test fixture connections. Set registers according to 10BASE-Te Link Pulse in Section 5.

GUID-20231130-SS0I-7R92-W1DK-2TF97MHK4QF3-low.svgFigure 3-9 10BASE-Te Link Pulse Example Waveform