SNLA343A April   2020  – July 2021 DP83825I

 

  1.   Trademarks
  2. 1Introduction
  3. 2Device Overview
  4. 3Merging DP83825 Onto Sitara Steps
    1. 3.1  Step 1 – DP83825 vs. DP83822
    2. 3.2  Step 2 – Check 8710A Pins with AM335
    3. 3.3  Step 3 – De-populate the LAN8710A from AM335 EVM - BBB
    4. 3.4  Step 4 – Check the AM335 (BBB) RMII Connection Pins
    5. 3.5  Step 5 – Check the DP83825 Connection Pins
    6. 3.6  Step 6 – PinMux Tool To Generate DTS/DTSI Files.
    7. 3.7  Step 7 – DP83822 Code Base Review
    8. 3.8  Step 8 – DP83825 Code Base Review / Patch Adaption
    9. 3.9  Step 9 – Patch the Linux uboot/kernel
    10. 3.10 Step 10 – Change the Menu Config
    11. 3.11 Step 11 – Building the Components (menuconfig/dtb/zimage)
    12. 3.12 Step 12 – (Optional) Important Fix for DTS Build
    13. 3.13 Step 13 – Copy the Built Files onto the SD Card
    14. 3.14 Step 14 – Register Checking for the DP83825.
    15. 3.15 Step 15 – Linux Command To Assist The Debug
    16. 3.16 Step 16 – Linux ethtool Command Dumps (example)
    17. 3.17 Step 17 – Linux dmesg to Check the Ethernet Driver Status.
    18. 3.18 Step 18 – Testing Result with Detail Log Analysis (Success Case).
    19. 3.19 Step 19 – YouTube Demonstration Video
  5. 4Required Hardware and Software
    1. 4.1 Hardware
    2. 4.2 Software
  6. 5References
  7. 6Revision History

2 Device Overview

Figure 2-1, is a Sitara MDIO / MII arch example. In the Figure 2-1, the MDIO is a control interface to control the Phy (example: DP83825), and the MII is an interface for the Data Channel between CPU and Phy.

GUID-D892BB82-31ED-49F2-8999-23D508ED24D0-low.png Figure 2-1 Sitara MDIO / MII Arch Example

Figure 2-2, show an example that the MII can be replaced by the other Ethernet Phy spec, for example (RMII, RGMII, SGMII and so on). MDIO control interface can be replaced by I2C/SPI.

While using TI Sitara platform to adapt the TI Phy, we are continuing with MDIO. The EMAC in the Figure 2-2 is an Ethernet MAC layer.

GUID-9111A99D-18E3-42EA-A6FC-78E45DECCA69-low.png Figure 2-2 Sitara MDIO / MII Detail Arch