SNLA344C March   2022  – October 2023 DP83826E , DP83826I

 

  1.   1
  2.   How and Why to Use the DP83826E for EtherCAT Applications
  3.   Trademarks
  4. 1Introduction
  5. 2EtherCAT® Specification Requirements and Recommendations
  6. 3Different Methods of Setting up the PHY
    1. 3.1 Using Strap Configuration to Set Up DP83826 PHY for EtherCAT® Configuration
      1. 3.1.1 Strapping Options
    2. 3.2 Using Serial Management Interface to Setup DP83826 PHY
      1. 3.2.1 Programming Options
  7. 4References
  8. 5Revision History

1 Introduction

When starting an EtherCAT® design, first review EtherCAT® Protocol, Physical Layer, EtherCAT® Processing Unit, FMMU, SyncManager, SII EEPROM, Distributed Clocks Data Sheet. This document describes how to connect an Ethernet PHY onto an EtherCAT® ESC. It also describes the needed interfaces between the ESC and Ethernet PHYs. These interfaces are the PHY Management Interface (PHY MI) and EtherCAT Interface, and are illustrated in Figure 1 from the previously referenced data sheet. In chapter 4 (Physical Layer Common Features) and 5 (Ethernet Physical Layer), the interface between the ESC and the PHY is described. Some key points to takeaway here include:

  • ESC in reset state has to leave the PHY disabled (No link connection until active ESC)
  • MII interface has special use for TX_CLK, COL, CRS, TX_ER pins; for details, see table 14 (Special/Unused MII Interface signals).
  • EtherCAT® has a special setup to determine Link Detection in several steps; see section 5.6 for details
  • LINK_MII signal, this is typically an LED output signal which indicate a 100 Mbit/s Full Duplex link
  • Enhanced link detection which is ensuring that the link signal is checked every approximately 10 µs; see section 5.6.2 for details