• The DSI transmitter must convey accurate DPI-type timing for HSS, and VSS packets only.
• Since Burst Mode does not utilize HSE and VSE packets to define the falling edge of the HSYNC/VSYNC signals, the serializer must be programmed to generate the desired sync widths with the DSI_HSW_CFG and DSI_VSW_CFG registers.
• The timing of the rising edge of each sync signal is defined by the received timing of the HSS/VSS DSI short packets (which also defines the horizontal and vertical back porch value for the video).
• The pixel transmission rate can be time compressed for each active video line. This allows sending each line at an arbitrarily high lane speed (within the maximum capability of the DSI receiver).
• The output pixel rate is defined by the REFCLK source applied to the DS90UB941AS-Q1.

Figure 2-3 Burst Mode Packet Structure.

It is important to note that the DSI source driver may need to be adjusted if it cannot meet the requirements of the DSI v1.3.1 standard for a given video configuration. For example, it is possible that a DSI source may send the correct packet structure for the selected DSI mode and video configuration, but does not meet the DPI timing requirements outlined above. In this case, output DPI timing may not meet expectations which can lead to timing errors at the display. It is important to verify the DSI source configuration with a MIPI DSI analyzer prior to applying the source to DS90UB941AS-Q1 in order to ensure that both the packet structure and packet timing are correct.