SNLA356 September   2020 DS90UB941AS-Q1 , DS90UH941AS-Q1

 

  1.   Abstract
  2.   Trademarks
  3. 1Introduction
  4. 2MIPI DSI Source Requirements
    1. 2.1 Supported DSI Modes
    2. 2.2 Clocking Rates and Clock Type
    3. 2.3 Blanking or Low Power Modes (BLLP)
    4. 2.4 DSI Packet Timing
      1. 2.4.1 Non-Burst Mode With Sync Pulses
      2. 2.4.2 Non-Burst Mode With Sync Events
      3. 2.4.3 Burst Mode
  5. 3Bring-Up and Debug Flow
  6. 4Example Bringup Scenarios
    1. 4.1 Discontinuous Clock
    2. 4.2 Missing Periodic Low Power Transitions
    3. 4.3 Incorrect DSI Packet Timing
    4. 4.4 THS-SKIP Configuration
    5. 4.5 End of Transmission Packets (EoTp)
    6. 4.6 Configuration of Sync Width for Event Mode/Burst Mode
  7. 5Summary
  8. 6References

4.1 Discontinuous Clock

When DS90UB941AS-Q1 is operated in DSI Reference Clock Mode, the DSI clock from the source is used to directly set the FPD-Link forward channel frequency and video PCLK rate. It is important to ensure that the DSI clock is continuous (no LP-11 transitions) at all times. For continuous clock mode, the clock lane remains in high-speed mode with a constant frequency at all times. For non-continuous clock mode, the clock lane may enter the LP-11 low power state between HS data packet transmissions.

Symptoms:

  • DSI_VC_DTYPE register reports correct data type for the video and:
    • Periodic flickering screen
    • Periodic loss of LOCK from the deserializer
    • Black screen

How to Verify:

  1. Check the DSI_VC_DTYPE register via I2C:
    1. Write 0x40 = 0x04 for DSI Port 0 or 0x40 = 0x08 for DSI Port 1
    2. Write 0x41 = 0x2A
    3. Read 0x42 (DSI_VC_DTYPE)
    4. The DSI_DTYPE is contained in bits 5:0

To verify that the DSI clock is continuous, the system designer can probe the DSI clock lane during video transmission. This can be done with a single ended probe attached between one of the data lane P/N nets and GND. The goal is to set the oscilloscope trigger to capture the LPTX amplitude only, while ignoring the HS data transmission.

During HS mode transmission, the clock is expected to have a common mode voltage between 150 mV-250 mV and a differential swing of 140 mV-270 mV.

During Low Power Mode (LP-11), the P/N clock lanes will no longer be differential. They will both transition to the LPTX high level output voltage of 0.95 V-1.3 V.

Set the oscilloscope trigger level to 800mV and monitor the clock lane activity. If the scope does not trigger from the 800mV level, then the DSI clock is continuous. The clock should show continuous toggling activity with a differential swing of ~140 mV - 27 0 mV and a common mode of ~150 mV-250 mV

Resolution:

The DSI source must be configured to enable DSI continuous clock mode. Consult the kernel driver manual for the DSI source for options to enable this behavior which is sometimes referred to a "High Power Mode". Some examples of flags in the DSI source driver pertaining to this configuration are:

  • sDeviceConfig.bEnableClkLaneHighPwrMode
  • dsi-video-clock-mode