SNLA423 March   2023 DP83826E

 

  1. 1Trademarks
  2. 2DP83826 Application Overview
  3. 3Troubleshooting the Application
    1. 3.1 Read and Check Register Values
    2. 3.2 Schematic and Layout Checklist
    3. 3.3 Component Checklist
    4. 3.4 Peripheral Pin Checks
      1. 3.4.1 Power Supplies
      2. 3.4.2 Probe the XI Clock
      3. 3.4.3 Probe the RESET_N Signal
      4. 3.4.4 Probe the Strap Pins During Initialization
      5. 3.4.5 Probe the Serial Management Interface Signals (MDC, MDIO)
      6. 3.4.6 Probe the MDI Signals
    5. 3.5 Link Quality Check
    6. 3.6 Built-In Self Test with Various Loopback Modes
    7. 3.7 Debugging MAC Interface
    8. 3.8 Tools and References
      1. 3.8.1 DP83826 Register Access
      2. 3.8.2 Extended Register Access
      3. 3.8.3 Application Note References
  4. 4Conclusion
  5. 5Revision History

3.5 Link Quality Check

After establishing a valid link, confirming the key status register values and visually verifing that the link LED is lit, the next data transfer debug step is to check the MAC Interface.

There are several possible sources of link problems:

  1. Link partner transmit problem
  2. Cable length and quality
  3. Clock quality of the 25 MHz reference clock
  4. MDI signal quality

IEEE compliance measurements can be made to verify the signaling. For details on these measurements, please refer to the application note DP83826 Ethernet Compliance Testing (SNLA239).

With the PHY powered and connected to a link partner, the following registers can be read from to determine the health of the link:

Table 3-6 Link Quality MSE Registers
CHANNEL REGISTER ADDRESS
A 0x225

For a given channel, read the register value to determine the MSE (Mean Square Error), convert to decimal, and refer to the following table to determine link quality:

Table 3-7 MSE Link Quality Ranges
LINK QUALITY MSE RANGE
Excellent < 522
Good 522 - 827
Poor > 827