SNLA423 March   2023 DP83826E

 

  1. 1Trademarks
  2. 2DP83826 Application Overview
  3. 3Troubleshooting the Application
    1. 3.1 Read and Check Register Values
    2. 3.2 Schematic and Layout Checklist
    3. 3.3 Component Checklist
    4. 3.4 Peripheral Pin Checks
      1. 3.4.1 Power Supplies
      2. 3.4.2 Probe the XI Clock
      3. 3.4.3 Probe the RESET_N Signal
      4. 3.4.4 Probe the Strap Pins During Initialization
      5. 3.4.5 Probe the Serial Management Interface Signals (MDC, MDIO)
      6. 3.4.6 Probe the MDI Signals
    5. 3.5 Link Quality Check
    6. 3.6 Built-In Self Test with Various Loopback Modes
    7. 3.7 Debugging MAC Interface
    8. 3.8 Tools and References
      1. 3.8.1 DP83826 Register Access
      2. 3.8.2 Extended Register Access
      3. 3.8.3 Application Note References
  4. 4Conclusion
  5. 5Revision History

3.4.3 Probe the RESET_N Signal

The reset input is active low. It is important to confirm that the controller is not driving the RESET_N signal low. Otherwise, the device will be held in reset and will not respond.