SNLA431 January   2024 DP83TC812R-Q1 , DP83TC812S-Q1

 

  1.   1
  2.   Trademarks
  3. 1Preface
  4.   Notational Conventions
  5. 2Related Documentation
  6. 3Support Resources
  7. 4Troubleshooting the PHY Application
    1. 4.1  Schematic and Layout Checklist
    2. 4.2  Verify Successful Power-up of PHY
    3. 4.3  Peripheral Pin Checks
      1. 4.3.1 Probe the RESET_N pin
      2. 4.3.2 Probe the INH pin
      3. 4.3.3 Probe the CLKOUT pin
      4. 4.3.4 Probe the Serial Management Interface (MDC, MDIO) Pins
    4. 4.4  Register Dump Comparison
    5. 4.5  Verifying Strap Configurations
    6. 4.6  Check the MDI Signal
    7. 4.7  Link Up Failed Common Issues
    8. 4.8  Signal Quality Check
    9. 4.9  Power Up Timing
    10. 4.10 Loopback Testing
    11. 4.11 Debugging the MAC Interface
    12. 4.12 Verify Open Alliance PMA Compliance
    13. 4.13 Tools and References
      1. 4.13.1 DP83TC812 Register Access
      2. 4.13.2 DP83TC812 USB2MDIO Scripts
      3. 4.13.3 Extended Register Access
      4. 4.13.4 Software and Driver Debug on Linux
        1. 4.13.4.1 Commonly Seen Linux Terminal Outputs
  8. 5Conclusion

4.3.4 Probe the Serial Management Interface (MDC, MDIO) Pins

If register read and write is successful, this section can be skipped.

If register read and write is unsuccessful, probe the MDC signal (pin 1) to maintain that there is a ≤20Mhz clock signal being sourced from the MAC. Additionally, the MDIO signal (pin 36) can be decoded using a logic analyzer as shown below.

Note, to access extended registers (those beyond 0x1F), the procedure given in section 8.4.15 of the data sheet must be used.

Table 4-3 SMI Protocol Structure

SMI Protocol

 <idle><start><op code><device addr><reg addr><turnaround><data><idle>

Read Register

<idle><01><10><AAAAA><RRRRR><Z0><XXXX XXXX XXXX XXXX><idle>

Write Register

 <idle><01><01><AAAAA><RRRRR><10><XXXX XXXX XXXX XXXX><idle>

GUID-20230801-SS0I-MZBB-ZXDW-LMNTKXBSRPHJ-low.png Figure 4-2 MDC/MDIO Write Example
Note: MDC/MDIO write operation for register 0xE = 0x0624 on PHY address 8.
GUID-20230801-SS0I-N9QX-R70Q-MB8QHSWRNXGN-low.png Figure 4-3 MDC/MDIO Read Example
Note: MDC/MDIO read operation on register 0x1 of PHY address 8.