SNLA437 December   2023 DP83822H , DP83822HF , DP83822I , DP83822IF , DP83826I

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1DP83822 Application Overview
  5. 2Troubleshooting the PHY Application
    1. 2.1  Schematic and Layout Checklist
    2. 2.2  Verify Successful Power-up of PHY
    3. 2.3  Read and Check Register Values
    4. 2.4  Peripheral Pin Checks
      1. 2.4.1 Probe the RESET_N Signal
      2. 2.4.2 Probe the RBIAS pin
      3. 2.4.3 Probe the Serial Management Interface (MDC, MDIO) Signals
      4. 2.4.4 Probe the MDI Signals
    5. 2.5  Verifying Strap Configurations During Initialization
    6. 2.6  Debugging Link Quality
    7. 2.7  Built-In Self Test With Various Loopback Modes
    8. 2.8  Debug the Fiber Connection
    9. 2.9  Debug the MAC Interface
    10. 2.10 Debug the Start of Frame Detect
    11. 2.11 Tools and References
      1. 2.11.1 DP83822 Register Access
      2. 2.11.2 Extended Register Access
      3. 2.11.3 Software and Driver Debug on Linux
        1. 2.11.3.1 Common Terminal Outputs and Solutions
  6. 3References

2.10 Debug the Start of Frame Detect

The IEEE 1588 indication pulse at the SFD can be delivered to any of the following pins: LED_0, LED_1 (GPIO1), COL (GPIO2), RX_D3 (GPIO3), INT/PWDN_N and CRS. The exact timing of the pulse can be adjusted via Register 0x003F.

GUID-D6EA01F3-5C29-4952-B89F-3548FD6A31CD-low.gif Figure 2-20 IEEE 1588 Message Timestamp Point

There are three registers that are able to control the routing of the IEEE 1588 transmit and receive indications. Register 0x003E is able to route both transmit and receive indications to LED_0 (GPIO1), COL (GPIO2), CRS and INT/PWDN_N. Two additional registers allow for additional pin selections and a centralized location for GPIO controls through the use of the IO MUX GPIO Control Registers, Register 0x0462 and Register 0x0463. After enabling/setting the RX_SFD and TX_SFD pins in registers IOCTRLx, write the following two registers:

  • Program (Register 0x0456 = value 0x000A)
  • Program (Register 0x04A0 = value 0x1080)
    • Note that register 0x04A0 is enabling "bit 7: WOL". This helps improve the accuracy of SFD detection and is not a must change. This does not cause PHY to detect WoL packets, as WoL function needs additional register configurations.
Note: A software reset has to be performed to load these register values (Register 0x001F = value 0x4000).