SNLA437 December   2023 DP83822H , DP83822HF , DP83822I , DP83822IF , DP83826I

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1DP83822 Application Overview
  5. 2Troubleshooting the PHY Application
    1. 2.1  Schematic and Layout Checklist
    2. 2.2  Verify Successful Power-up of PHY
    3. 2.3  Read and Check Register Values
    4. 2.4  Peripheral Pin Checks
      1. 2.4.1 Probe the RESET_N Signal
      2. 2.4.2 Probe the RBIAS pin
      3. 2.4.3 Probe the Serial Management Interface (MDC, MDIO) Signals
      4. 2.4.4 Probe the MDI Signals
    5. 2.5  Verifying Strap Configurations During Initialization
    6. 2.6  Debugging Link Quality
    7. 2.7  Built-In Self Test With Various Loopback Modes
    8. 2.8  Debug the Fiber Connection
    9. 2.9  Debug the MAC Interface
    10. 2.10 Debug the Start of Frame Detect
    11. 2.11 Tools and References
      1. 2.11.1 DP83822 Register Access
      2. 2.11.2 Extended Register Access
      3. 2.11.3 Software and Driver Debug on Linux
        1. 2.11.3.1 Common Terminal Outputs and Solutions
  6. 3References

2.6 Debugging Link Quality

There are several possible sources of link problems:

  • Cable length and quality
  • Clock quality of the 25 MHz reference clock
  • MDI signal quality
  • Which advertising mode the PHY is in

To verify that a link-up is successful, confirm that Register 0x0001 Bit [2] is read as high [1] and visually inspect if the link LED is lit if applicable. The link quality could cause packet losses and CRC errors despite successful link-up, therefore it is a good practice to always verify the signal quality between the PHY and link partner to ensure signal integrity.

After running through all the previous steps to ensure the PHY functions successfully, the most common link issues happen with the cable or the connector. To find which advertising mode the PHY is in, Register 0x0004 Auto-Negotiation Advertisement Register (ANAR) can be read. For the link partner, Register 0x0005 Auto-Negotiation Link Partner Ability Register (ANLPAR) can be read.

With the PHY powered and connected to a link partner, the following registers can be read from to determine the health of the link:

Table 2-6 Link Quality MSE Registers
Channel Register Address
A 0x218

For a given channel, read the register value to determine the MSE (Mean Square Error), convert to decimal, and see Table 2-7 to determine link quality.

Table 2-7 MSE Link Quality Ranges
Link Quality Register Address
Excellent < 522
Good 522 - 827
Poor > 827

A Time-Domain Reflectometry (TDR) test can also be performed on the PHY to detect problems within the wire's connections and where the fault occurred. For more details regarding different TDR configurations and test modes as well as how to run a TDR test on the PHY, see How to use the TDR Feature of DP83822.