SNLA438 September   2023 DP83822H , DP83822HF , DP83822I , DP83822IF , DP83826E , DP83826I , DP83867CS , DP83867E , DP83867IS , DP83869HM

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction
  5. 2PROFINET Specification Requirements
  6. 3Ethernet PHY Setup
    1. 3.1 DP83822
      1. 3.1.1 DP83822 Hardware Bootstrap Configurations
      2. 3.1.2 DP83822 Register Configuration
    2. 3.2 DP83826
      1. 3.2.1 DP83826 Hardware Bootstrap Configuration
      2. 3.2.2 DP83826 Register Configuration
    3. 3.3 DP83867
      1. 3.3.1 DP83867 Hardware Bootstrap Configurations
      2. 3.3.2 DP83867 Register Configuration
    4. 3.4 DP83869
      1. 3.4.1 DP83869 Hardware Bootstrap Configurations
      2. 3.4.2 DP83869 Register Configuration
  7. 4Summary
  8. 5References

3.3.1 DP83867 Hardware Bootstrap Configurations

The DP83867 uses many of the functional pins as strap options to place the device into specific modes of operation. The values of these pins are sampled at power up or hard reset. During software resets, the strap options are internally reloaded from the values sampled at power up or hard reset.

GUID-FFD00AF3-5E21-4A36-8D18-ACADFEDEEBAA-low.gif Figure 3-6 Strap Circuit
Table 3-6 DP83867 100Base-TX Strapping
DP83867 100Base-TX/1000Base-T Pin RH(kΩ) RL(kΩ) Remarks

MAC Interface: RGMII,

100Base-TX/1000Base-X,

Auto-Negotiation Enabled

 RX_CTRL 5.76 2.49 Autoneg enable
GPIO_0 Open Open

RGMII TX/RX Clock Skew set to default value (2.0 ns)

Advertise 100/1000 speed only
GPIO_1 Open Open
LED_2 Open Open
LED_1 2.49 Open
LED_0 Open Open

SGMII Disable

Mirror Mode Disable