SNLA445 Application note

SNLA445 November 2023 LMK6H

5.1 LMK6H Test Results Summary

Table 5-1 is the PCIe compliance results summary for the LMK6H phase noise analysis, which demonstrates the jitter compliance of the device for PCIe Gen 1 through 6, noise folds 0 and 3, and Common Clock (CC) and Separate Reference No Spread (SRNS) clock architectures.

A PCIe jitter spec or time domain calculation can have one of the following statuses:

PASS: within specifications/limits
FAIL: outside specifications/limits
N/A: no specifications/limits available

Table 5-1 LMK6H PCIe Tool Test Results Summary - Frequency Domain

Jitter Filter	Clock Arch.	Noise Fold	Min (fs)	Max (fs)	Limit (fs)	Status
PCIe1	CC	0	0.0	1,384	86,000	PASS
PCIe1	CC	3	0.0	1,826	86,000	PASS
PCIe2	CC	0	48	152	3,100	PASS
	CC	3	63	199	3,100	PASS
	SRNS	0	59	157	N/A	N/A
	SRNS	3	79	207	N/A	N/A
PCIe3	CC	0	16	46	1,000	PASS
	CC	3	21	60	1,000	PASS
	SRNS	0	18	50	N/A	N/A
	SRNS	3	24	65	N/A	N/A
PCIe4	CC	0	16	46	500.0	PASS
	CC	3	21	60	500.0	PASS
	SRNS	0	18	50	N/A	N/A
	SRNS	3	24	65	N/A	N/A
PCIe5	CC	0	4	20	150.0	PASS
	CC	3	5	25	150.0	PASS
	SRNS	0	4	20	N/A	N/A
	SRNS	3	5	27	N/A	N/A
PCIe6	CC	0	4	12	100.0	PASS
	CC	3	5	15	100.0	PASS
	SRNS	0	5	15	N/A	N/A
	SRNS	3	7	19	N/A	N/A

Table 5-2 is the PCIe compliance summary for the LMK6H time domain analysis which demonstrates the time domain compliance of the device.

Table 5-2 LMK6H PCIe Tool Test Results Summary - Time Domain

Calculation	Min	Avg	Max	Limit	Status
V_cross	398.77	403.0	406.87	250 mV to 550 mV	PASS
V_high	684.703	684.703		150 mV	PASS
V_low		-80.0	-80.0	-150 mV	PASS
Period	9.994	10.0	10.012	9.847 ns to 10.203 ns	PASS
Duty Cycle	50.279	50.377	50.459	40% to 60%	PASS
Overshoot Voltage		20.79	27.36	300 mV	PASS
Undershoot Voltage		-19.66	-28.08	-300 mV	PASS
Rising Edge Rate	3.028	3.164	3.374	0.6 V/ns to 4 V/ns	PASS
Falling Edge Rate	2.369	2.536	2.703	0.6 V/ns to 4 V/ns	PASS