SNLA447 Application note

SNLA447 November 2023 LMK6H , LMKDB1108 , LMKDB1120

5.1 LMK6H and LMKDB1xxx Test Results Summary

Table 5-1 is the PCIe compliance results summary for the LMK6H and LMKDB1xxx phase noise analysis, which demonstrates the jitter compliance of the device for PCIe Gen 1 through 6, noise folds 0 and 3, and clock architectures Common Clock (CC) and Separate Reference No Spread (SRNS).

A PCIe jitter spec or time domain calculation can have one of the following statuses:

PASS: within specifications/limits
FAIL: outside specifications/limits
N/A: no specifications/limits available

Table 5-1 LMK6H and LMKDB1xxx PCIe Tool Test Results Summary - Frequency Domain

Jitter Filter	Clock Arch.	Noise Fold	Min (fs)	Max (fs)	Limit (fs)	Status
PCIe1	CC	0	0.0	1,385	86,000	PASS
PCIe1	CC	3	0.0	1,826	86,000	PASS
PCIe2	CC	0	46	145	3,100	PASS
	CC	3	57	181	3,100	PASS
	SRNS	0	59	49	N/A	N/A
	SRNS	3	73	60	N/A	N/A
PCIe3	CC	0	15	43	1,000	PASS
	CC	3	19	54	1,000	PASS
	SRNS	0	18	49	N/A	N/A
	SRNS	3	22	60	N/A	N/A
PCIe4	CC	0	18	43	500.0	PASS
	CC	3	22	54	500.0	PASS
	SRNS	0	18	49	N/A	N/A
	SRNS	3	22	60	N/A	N/A
PCIe5	CC	0	3	18	150.0	PASS
	CC	3	4	23	150.0	PASS
	SRNS	0	4	19	N/A	N/A
	SRNS	3	5	24	N/A	N/A
PCIe6	CC	0	4	11	100.0	PASS
	CC	3	5	14	100.0	PASS
	SRNS	0	5	15	N/A	N/A
	SRNS	3	6	18	N/A	N/A

Table 5-2 is the PCIe compliance summary for the LMK6H and LMKDB1xxx time domain analysis which demonstrates the time domain compliance of the device.

Table 5-2 LMK6H and LMKDB1xxx PCIe Tool Test Results Summary - Time Domain

Calculation	Min	Avg	Max	Limit	Status
V_cross	277.85	291.29	304.06	250 mV to 550 mV	PASS
V_high	664.188	664.188		150 mV	PASS
V_low		3.625	3.625	-150 mV	PASS
Period	9.992	10.001	10.016	9.847 ns to 10.203 ns	PASS
Duty Cycle	49.957	50.064	50.217	40% to 60%	PASS
Overshoot Voltage		42.9	56.19	300 mV	PASS
Undershoot Voltage		-53.95	-72.38	-300 mV	PASS
Rising Edge Rate	3.451	3.662	3.897	0.6 V/ns to 4 V/ns	PASS
Falling Edge Rate	3.374	3.579	3.809	0.6 V/ns to 4 V/ns	PASS