SNLA448 November   2023 LMK3H0102

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction
  5. 2Test Setup
  6. 3Test Procedure
  7. 4Explanation of TI's PCIe Compliance Tool
  8. 5LMK3H0102 Test Results
    1. 5.1 LMK3H0102 Test Results Summary
    2. 5.2 PCIe Tool Input File Waveforms for the LMK3H0102 Family
    3. 5.3 LMK3H0102 Detailed Jitter Measurements
  9. 6Summary
  10. 7References

5.2 PCIe Tool Input File Waveforms for the LMK3H0102 Family

Figure 5-1 illustrates output phase noise curve of the LMK3H0102 with a 100-MHz LP-HCSL –0.5% down-spread SSC output.Figure 5-2 illustrates output phase noise curve of the LMK3H0102 with a 100-MHz LP-HCSL –0.5% down-spread SSC output. Figure 5-3 illustrates the input trace waveform. All of these waveforms are inputted into TI's PCIe Compliance Tool (found within TI's TICS Pro Software, more information in Section 4) to determine PCIe compliance.

GUID-20231110-SS0I-KF4N-JNWP-HBW9VVZRMPX4-low.png Figure 5-1 Output Phase Noise Curve from the LMK3H0102, 100-MHz LP-HCSL, No SSC
GUID-20231110-SS0I-CJX0-QRHN-840S9TB16TGQ-low.png Figure 5-2 Output Phase Noise Curve from the LMK3H0102, 100-MHz LP-HCSL, –0.5% Down-Spread SSC
GUID-20231110-SS0I-7NNF-W5S5-WLLC6JGWJGZS-low.png Figure 5-3 Output Time Domain Plot from the LMK3H0102