SNLA474A October   2024  – October 2024 DS90UB971-Q1

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1 Introduction
  5. 2 Typical Test Standards Overview
    1. 2.1 ISO 10605 Standard
    2. 2.2 Performance Status Categorization
  6. 3 FPD-Link Hardware Optimizations
    1. 3.1 Connector Grounding
    2. 3.2 PCB to Enclosure Grounding
    3. 3.3 MODE Selection
  7. 4 FPD-Link Software Optimizations
    1. 4.1 LOCK Detection Tuning
    2. 4.2 Parity Error Handling
    3. 4.3 Forward Error Correction
      1. 4.3.1 FEC Test Capabilities
  8. 5 Optimization Test Data
    1. 5.1 Baseline Hardware - No Software Optimization
    2. 5.2 Optimized Hardware - No Software Optimization
    3. 5.3 Optimized Hardware and Software
  9. 6 Example Scripts for Software Optimization
  10. 7 Additional System Level Software Options
  11. 8 Summary
  12. 9 References
  13. 10Revision History

5 Optimization Test Data

To illustrate the impact of hardware and software optimizations on system level ESD performance, TI conducted ISO 10605 testing under multiple deserializer configurations using the FPD-Link IV DS90UB971-Q1 and DS90UB9702-Q1 devices:

  • Basic hardware design/No software optimizations
  • Optimized hardware design/No software optimizations
  • Optimized hardware design + Software optimizations
The tests were conducted using a DS90UB971-Q1 camera module operating at 7.55Gbps, connected to the deserializer hardware (DS90UB9702-Q1) via a 1.5m Dacar 302 cable. The deserializer system is housed inside a metal enclosure to emulate a typical ECU subsystem design. The deserializer enclosure is connected to the table GND plane, and the cable as well as the camera module are suspended above the ground plane using an insulating block.

The goal of this ISO 10605 testing is to emulate a typical OEM EMC approval setup, where performance of the system is categorized into Class A, B, C, or D during ESD strike events. By testing three systems with incremental hardware and software optimizations in place, a typical improvement trend is realized. This testing does not reflect the precise results that are expected in every system design; rather the testing is meant to demonstrate relative performance improvement that is possible through optimized hardware and software design.