The FPD-Link ADAS forward channel protocol packs video payload data as well as other information including GPIO, I2C, status, clocking, and more into serial frames which are sent to a downstream deserializer. To properly decode the incoming data frames, the FPD-Link receiver must both lock to the incoming high speed signal by determining the correct transition rate of the data, and the receiver must properly determine the alignment of the incoming data frames (for example, the beginning and end of each serial frame). To accomplish the task of alignment, the FPD-Link ADAS serializer inserts a multi-frame synchronization data pattern called the Decode Cycle Array (DCA) sequence of 130 characters within the forward channel data stream, as well as two dedicated clocking bits per frame (CLK0/CLK1).

After initial LOCK has been established, the deserializer continuously monitors the incoming serial frames to detect the expected position of the two clocking bits within each frame, and the 130 frame DCA encoding bit pattern. By default, the FPD-Link LOCK signal drops upon the detection of three errors in the clocking and encoding bits over the span of 130 incoming frames. While this default behavior does provide a good leading indicator of an increased BER in the link, the default behavior also causes the link to be highly sensitive to transient error events like ESD strikes. Additionally, note that transient errors can occur in the clocking or encoding bits of the FPD frame without disrupting any application level functionality. So long as errors are transient, the FPD-Link receiver maintains operation and alignment automatically.

To improve robustness of the link under ESD stress, TI recommends to increase the LINK_ERR_THRESH setting within the deserializer which increases the number of errors that must be detected within each 130 frame period before the deserializer drops LOCK and begins re-acquisition. This threshold configuration can be found in register 0xB9 (LINK_ERROR_COUNT). For the configured threshold to take effect, LINK_ERR_COUNT_EN must also be set to 1.

Another optimization which can be applied to decrease sensitivity of the LOCK drop algorithm is to disable the clock bit error detection as part of the link error counter. By configuring register 0xB6 = 0x1C, detection of the clocking bits is no longer used as a marker to drop LOCK. Only the repeating 130 frame DCA encoding pattern is used for LOCK drop detection with this setting.