SNLA474A October   2024  – October 2024 DS90UB971-Q1

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1 Introduction
  5. 2 Typical Test Standards Overview
    1. 2.1 ISO 10605 Standard
    2. 2.2 Performance Status Categorization
  6. 3 FPD-Link Hardware Optimizations
    1. 3.1 Connector Grounding
    2. 3.2 PCB to Enclosure Grounding
    3. 3.3 MODE Selection
  7. 4 FPD-Link Software Optimizations
    1. 4.1 LOCK Detection Tuning
    2. 4.2 Parity Error Handling
    3. 4.3 Forward Error Correction
      1. 4.3.1 FEC Test Capabilities
  8. 5 Optimization Test Data
    1. 5.1 Baseline Hardware - No Software Optimization
    2. 5.2 Optimized Hardware - No Software Optimization
    3. 5.3 Optimized Hardware and Software
  9. 6 Example Scripts for Software Optimization
  10. 7 Additional System Level Software Options
  11. 8 Summary
  12. 9 References
  13. 10Revision History

4.3.1 FEC Test Capabilities

Supporting serializer and deserializer devices contain verification features to check FEC functionality is operational. The serializer can inject FEC errors via register command, and the deserializer provides diagnostics for the number of ECC1/ECC2 FEC errors detected in the FPD-Link channel. Note that these are not the same as ECC1/ECC2 CSI-2 errors reported by the CSI_RX_STS register. 

board.WriteI2C(serAddr,0x76,0x01) # Force 1x FPD ECC1 error (Correctable) 
board.WriteI2C(serAddr,0x76,0x02) # Force 1x FPD ECC2 error (Detectable)

Deserializer diagnostic counters for FEC errors are port-specific. Select the desired RX port with register 0x4C before reading diagnostics.

board.WriteI2C(desAddr,0x4C,0x01) # Select RX port 0
board.ReadI2C(desAddr,0x48) # Read back count of FPD ECC1 Errors (Clear on Read)
board.ReadI2C(desAddr,0x49) # Read back count of FPD ECC2 Errors (Clear on Read)