SNLA474A October 2024 – October 2024 DS90UB971-Q1
Select FPD-Link devices within the FPD-Link III and FPD-Link IV product families include forward error correction (FEC) functionality within the FPD-Link forward channel path. Forward error correction utilizes unoccupied channel bandwidth to send error correcting code words along with the forward channel data payload which allows the downstream deserializer to correct transient errors. FEC functionality is available on the following devices:
FEC functionality is not available on the following devices:
To utilize FEC functionality, both the serializer and deserializer device within the link pair must support FEC.
There are three selectable FEC modes available with different code sizes for the inserted error correcting codes (ECC):
When FEC is enabled, the serializer sends multiple (X) data frames, followed by multiple (Y) frames containing error correcting codes (ECC) in sequence. The error correcting code chunks (Y) protect CSI-2 data, GPIO data, and I2C data by allowing the deserializer to detect 2-bit errors, and correct 1-bit errors within the data chunk (X) much like the data protection within the packet header for CSI-2 data.
Each FEC mode defines a ratio of (X) data frames and (Y) ECC frames sent within a 130 frame DCA sequence. The 6-bit mode protects smaller chunks of data, but correction codes are sent more frequently. The 8-bit mode protects larger chunks of data, with correction codes sent less frequently. The ratios are defined below:
FEC Mode | Number of Data Frames (X) | Number of ECC Frames (Y) | ECC Frames Per DCA Sequence | Data Frames Per DCA Sequence | FEC Overhead |
---|---|---|---|---|---|
6-bit | 20 | 6 | 30 | 100 | 23% |
7-bit | Alternating 36, 37 | 7 | 21 | 109 | 16% |
8-bit | 57 | 8 | 16 | 114 | 12% |
FEC overhead reduces the allowable payload capability for video in the FPD-Link forward channel pipeline. Care must be taken to verify that the link video bandwidth after FEC is enabled can meet the application's needs.
Device | FPD-Link Rate (Gbps) | Max CSI-2 Bandwidth (Gbps) | FEC Mode | Max CSI-2 Bandwidth FEC Enabled (Gbps) |
---|---|---|---|---|
DS90UB971-Q1 | 7.55 | 6 | 6-bit | 4.8 |
DS90UB971-Q1 | 7.55 | 6 | 7-bit | 5.1 |
DS90UB971-Q1 | 7.55 | 6 | 8-bit | 5.3 |
DS90UB953-Q1 | 4 | 3.2 | 6-bit | 2.6 |
DS90UB953-Q1 | 4 | 3.2 | 7-bit | 2.7 |
DS90UB953-Q1 | 4 | 3.2 | 8-bit | 2.8 |
DS90UB935-Q1 | 4 | 2.528 | 6-bit | 2.528 (Lesser of 2.528Gbps and 3.2Gbps/1.23) |
DS90UB935-Q1 | 4 | 2.528 | 7-bit | 2.528 (Lesser of 2.528Gbps and 3.2Gbps/1.16) |
DS90UB935-Q1 | 4 | 2.528 | 8-bit | 2.528 (Lesser of 2.528Gbps and 3.2Gbps/1.12) |
To enable FEC functionality, configure deserializer register 0x4A (port specific):
The deserializer notifies the serializer to enter FEC mode via the back channel automatically.