SNLA474A October   2024  – October 2024 DS90UB971-Q1

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1 Introduction
  5. 2 Typical Test Standards Overview
    1. 2.1 ISO 10605 Standard
    2. 2.2 Performance Status Categorization
  6. 3 FPD-Link Hardware Optimizations
    1. 3.1 Connector Grounding
    2. 3.2 PCB to Enclosure Grounding
    3. 3.3 MODE Selection
  7. 4 FPD-Link Software Optimizations
    1. 4.1 LOCK Detection Tuning
    2. 4.2 Parity Error Handling
    3. 4.3 Forward Error Correction
      1. 4.3.1 FEC Test Capabilities
  8. 5 Optimization Test Data
    1. 5.1 Baseline Hardware - No Software Optimization
    2. 5.2 Optimized Hardware - No Software Optimization
    3. 5.3 Optimized Hardware and Software
  9. 6 Example Scripts for Software Optimization
  10. 7 Additional System Level Software Options
  11. 8 Summary
  12. 9 References
  13. 10Revision History

4.2 Parity Error Handling

In addition to multi-frame encoding and clock error checks in the FPD-Link forward channel frames, each FPD-Link frame also includes known parity. This means that each incoming frame has an even number of 1s which is verified by the deserializer in real time. If the deserializer recognizes an incoming FPD frame has an odd number of 1s, then the deserializer can flag an error and increment a parity error counter for diagnostic purposes.

By default, ADAS deserializer are configured to discard FPD-Link forward channel frames which contain a parity error, meaning that no information contained within that frame is forwarded to downstream data paths. While this default behavior can prevent error propagation, the default behavior also increases sensitivity to transient errors which can have no impact on the application. Consider an example where an incoming FPD-Link frame has a single bit error causing a parity error to be flagged.

Parity Error Example Figure 4-2 Parity Error Example

In this example, a bit error impacted one of the forward channel GPIO slots within the FPD-Link frame. As a result, the number of 1s in the frame changes to an odd value and the deserializer discards the entire packet. However this kind of transient error in one of the frame clocking bits can be tolerated without breaking LOCK or losing frame boundaries. Additionally, this particular error did not affect any of the CSI-2 video data within the frame. Depending on the application use case, this error can have no impact on any aspect of the system whatsoever (for example if no forward channel GPIO are utilized by the application).

FPD-Link III and IV CSI-2 ADAS deserializer products can be configured to not discard packets with parity errors by setting DISCARD_ON_PAR_ERR to 0 in the PORT_CONFIG2 register. When this setting is disabled, sensitivity to transient error events is reduced which can help significantly in achieving class A performance during immunity testing.

Allowing packets with parity errors to be processed rather than discarded does not imply that corrupted video data can be passed through the deserializer unnoticed. This is because FPD-Link ADAS devices operate by tunneling CSI-2 packets from end to end. CSI-2 payload and checksum are both passed unaltered through the serializer and deserializer before reaching the downstream application processor. No re-calculation is done for the CSI-2 payload checksum (CRC). As a result, bit errors in the FPD-Link channel that do corrupt video pixel data cause the corresponding CSI-2 packet to fail CRC checking at the final destination. The application processor can then decide how best to handle the error depending on the application needs.

CSI-2 Packet Tunneling Figure 4-3 CSI-2 Packet Tunneling