SNLS416D June   2012  – January 2015 DS90UB927Q-Q1

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  DC Electrical Characteristics
    6. 6.6  AC Electrical Characteristics
    7. 6.7  Electrical Characteristics: DC and AC Serial Control Bus
    8. 6.8  Timing Requirements for the Serial Control Bus
    9. 6.9  Timing Requirements - DC and AC Serial Control Bus Characteristics
    10. 6.10 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  High-Speed Forward Channel Data Transfer
      2. 7.3.2  Low-Speed Back Channel Data Transfer
      3. 7.3.3  Common Mode Filter Pin (CMF)
      4. 7.3.4  Video Control Signals
      5. 7.3.5  EMI Reduction Features
        1. 7.3.5.1 LVCMOS VDDIO Option
      6. 7.3.6  Built-In Self Test (BIST)
        1. 7.3.6.1 BIST Configuration and Status
        2. 7.3.6.2 Sample BIST Sequence
      7. 7.3.7  Forward Channel and Back Channel Error Checking
      8. 7.3.8  Internal Pattern Generation
        1. 7.3.8.1 Pattern Options
        2. 7.3.8.2 Color Modes
        3. 7.3.8.3 Video Timing Modes
        4. 7.3.8.4 External Timing
        5. 7.3.8.5 Pattern Inversion
        6. 7.3.8.6 Auto Scrolling
      9. 7.3.9  Remote Auto Power-Down Mode
      10. 7.3.10 Input RxCLKIN Loss Detect
      11. 7.3.11 Serial Link Fault Detect
      12. 7.3.12 Interrupt Pin (INTB)
      13. 7.3.13 General-Purpose I/O
        1. 7.3.13.1 GPIO[3:0]
        2. 7.3.13.2 GPIO[8:5]
      14. 7.3.14 I2S Audio Interface
        1. 7.3.14.1 I2S Transport Modes
        2. 7.3.14.2 I2S Repeater
      15. 7.3.15 Additional Features
    4. 7.4 Device Functional Modes
      1. 7.4.1 Power Down (PDB)
      2. 7.4.2 Backward Compatible Mode
      3. 7.4.3 Low Frequency Optimization (LFMODE)
      4. 7.4.4 FPD-Link Input Frame and Color Bit Mapping Select
      5. 7.4.5 Repeater
        1. 7.4.5.1 Repeater Configuration
        2. 7.4.5.2 Repeater Connections
          1. 7.4.5.2.1 Repeater Fan-Out Electrical Requirements
    5. 7.5 Programming
      1. 7.5.1 Serial Control Bus
    6. 7.6 Register Maps
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
    3. 8.3 System Examples
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 CML Interconnect Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Trademarks
    3. 11.3 Electrostatic Discharge Caution
    4. 11.4 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

8 Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.

8.1 Application Information

The DS90UB927Q-Q1, in conjunction with the DS90UB928Q-Q1 or DS90UB926Q-Q1, is intended for interface between a host (graphics processor) and a display, supporting 24-bit color depth (RGB888) and high definition (720p) digital video format. It can receive an 8-bit RGB stream with a pixel clock rate up to 85 MHz together with three control bits (VS, HS and DE) and four I2S audio streams.

8.2 Typical Application

Figure 29 shows a typical application of the DS90UB927Q-Q1 serializer for an 85-MHz 24-bit Color Display Application. The 5 LVDS input pairs require external 100Ω terminations. The CML outputs must have an external 0.1-µF AC coupling capacitor on the high speed serial lines. The serializer has internal CML termination on its high speed outputs.

Bypass capacitors should be placed near the power supply pins. At a minimum, four (4) 4.7-µF capacitors should be used for local device bypassing. Ferrite beads are placed on the two sets of supply pins (VDD33 and VDDIO) for effective noise suppression. The interface to the graphics source is LVDS. The VDDIO pins may be connected to 3.3 V or 1.8 V. A capacitor and resistor are placed on the PDB pin to delay the enabling of the device until power is stable.

UB927_TypApp.gifFigure 29. Color Display Typical Connection Diagram

8.2.1 Design Requirements

For the typical design application, use the following as input parameters.

Table 6. Design Parameters

DESIGN PARAMETER EXAMPLE VALUE
VDDIO 1.8 V or 3.3 V
VDD33 3.3 V
AC Coupling Capacitor for DOUT± 100 nF
PCLK Frequency 85 MHz

8.2.2 Detailed Design Procedure

Figure 29 shows a typical application of the DS90UB927Q-Q1 serializer for an 85-MHz 24-bit Color Display Application. The CML outputs must have an external 0.1-μF AC coupling capacitor on the high speed serial lines. Bypass capacitors are placed near the power supply pins. At a minimum, six 4.7-μF capacitors and two additional 1-μF capacitors should be used for local device bypassing. Ferrite beads are placed on the two VDDs (VDD33 and VDDIO) for effective noise suppression. An RC delay is placed on the PDB signal to delay the enabling of the device until power is stable.

8.2.3 Application Curves

48stream.gifFigure 30. Serializer Output Stream with 48-MHz Input Clock
48eye.gifFigure 31. Serializer Eye with 48-MHz Input Clock

8.3 System Examples

UB927_AppsDiagram.gifFigure 32. Color Display Application Diagram
30193316.gifFigure 33. Megapixel Camera Application Diagram