DATA SHEET
DS125BR111 Low Power 12.5 Gbps 1-Lane Linear Repeater with Equalization
1 Features
- Low 65 mW/Channel (typ) Power Consumption
- Supports Link Training
- Supports Out-of-Band (OOB) Signaling
- Advanced Signal Conditioning I/O
- Receive CTLE up to 10 dB at 6 GHz
- Linear Output Driver
- Output Voltage Range over 1200 mV
- Programmable via Pin Selection, EEPROM, or SMBus Interface
- Single Supply Voltage: 2.5 V or 3.3 V
- −40°C to 85°C Operating Temperature Range
- Flow-thru Pinout in 4 mm × 4 mm 24-pin Leadless WQFN Package
2 Applications
- SAS-1/2/3 and SATA-1/2/3
- PCI Express 1/2/3
- Other Proprietary Interfaces up to 12.5 Gbps
3 Description
The DS125BR111 is an extremely low power high performance repeater/redriver designed to support 1-lane carrying high speed interface up to 12.5 Gbps. The receiver's continuous time linear equalizer (CTLE) provides a boost of 3-10 dB at 6 GHz in each channel. When operating in SAS-3 or PCIe Gen-3 applications, the DS125BR111 preserves transmit signal characteristics allowing the host controller and the end point to negotiate transmit equalizer coefficients. Transparency to the link training protocol maximizes the flexibility of the physical placement of the device within the interconnect and improves overall channel performance.
The programmable settings can be applied easily via pins, software (SMBus or I2C), or loaded via an external EEPROM. In EEPROM mode, the configuration information is automatically loaded on power up, which eliminates the need for an external microprocessor or software driver.
Device Information(1)
| PART NUMBER | PACKAGE | BODY SIZE (NOM) |
|---|---|---|
| DS125BR111 | WQFN (24) | 4.00mm x 4.00mm |
- For all available packages, see the orderable addendum at the end of the datasheet.
4 Simplified Schematic
5 Revision History
Changes from B Revision (July 2014) to C Revision
- Changed data sheet flow and layout to conform with new TI standards. Added the following sections: Application and Implementation; Power Supply Recommendations; Layout; Device and Documentation Support; Mechanical, Packaging, and Ordering Information Go
Changes from A Revision (January 2014) to B Revision
- Changed Features Go
Changes from * Revision (April 2013) to A Revision
- Changed layout of National Data Sheet to TI formatGo
6 Pin Configuration and Functions
24 Pin
Package RTW
Top View
The center DAP on the package bottom is the only device GND connection. This pad must be connected to GND through multiple (minimum of 4) vias to ensure optimal electrical and thermal performance.
Pin Functions
| PIN | I/O | DESCRIPTION | |
|---|---|---|---|
| NAME | NO. | ||
| DIFFERENTIAL HIGH SPEED I/O | |||
| INB+, INB- | 11, 12 | I | Inverting and non-inverting CML differential inputs to the equalizer. On-chip 50 Ω termination resistor connects INB+ to VDD and INB- to VDD when enabled by RXDET control logic. AC coupling required on high-speed I/O |
| OUTB+, OUTB- | 20, 19 | O | Inverting and non-inverting 50 Ω driver outputs. Compatible with AC coupled CML inputs. AC coupling required on high-speed I/O |
| INA+, INA- | 24, 23 | I | Inverting and non-inverting CML differential inputs to the equalizer. On-chip 50 Ω termination resistor connects INA+ to VDD and INA- to VDD when enabled by RXDET control logic. AC coupling required on high-speed I/O |
| OUTA+, OUTA- | 7, 8 | O | Inverting and non-inverting 50 Ω driver outputs. Compatible with AC coupled CML inputs. AC coupling required on high-speed I/O |
| CONTROL PINS — SHARED (LVCMOS) | |||
| ENSMB | 3 | I, 4-LEVEL, LVCMOS |
System Management Bus (SMBus) enable Pin Tie 1 kΩ to VDD = Register Access SMBus Slave mode FLOAT = Read External EEPROM (Master SMBus Mode) Tie 1 kΩ to GND = Pin Mode |
| ENSMB = Float or 1 (SMBus MODEs) | |||
| SCL | 5 | I, LVCMOS, O, OPEN Drain |
ENSMB Master or Slave mode SMBus clock input Pin is enabled (slave mode). Clock output when loading EEPROM configuration (master mode). |
| SDA | 4 | I, LVCMOS, O, OPEN Drain |
ENSMB Master or Slave mode The SMBus bidirectional SDA Pin is enabled. Data input or open drain output. External pull-up required as per SMBus protocol (typically in the 2 kΩ to 5 kΩ range). This pin is 3.3 V-tolerant. |
| AD0-AD3 | 10, 9, 2, 1 | I, LVCMOS | ENSMB Master or Slave mode SMBus Slave Address Inputs. In SMBus mode, these Pins are the user set SMBus slave address inputs. |
| READEN | 17 | I, LVCMOS | ENSMB = Float: When using an External EEPROM, a logic low on this pin starts the load from the external EEPROM ENSMB = 1: When using SMBus Slave Mode the VOD_SEL/READEN pin must be tied Low for the AD[3:0] to be active. If this pin is tied High or Floated an address of 0xB0 will be used for the DS125BR111. |
| DONE | 18 | O, LVCMOS | When using an External EEPROM (ENSMB = Float), Valid Register Load Status Output HIGH = External EEPROM load failed or incomplete LOW = External EEPROM load passed |
| ENSMB = 0 (PIN MODE) | |||
| EQA0 EQB0 |
10 1 |
I, 4-LEVEL, LVCMOS |
EQA0 and EQB0 control the level of equalization of the A/B directions. The Pins are defined as EQx0 only when ENSMB is de-asserted (low). When ENSMB goes high the SMBus registers provide independent control of each channel. See Table 4. |
| EQA1 EQB1 |
9 2 |
I, 4-LEVEL, LVCMOS |
EQA1 and EQB1 are not used in the DS125BR111 design. These pins should always be tied to GND. |
| VODA_DB | 4 | I, 4-LEVEL, LVCMOS |
VODA_DB controls the CHA output amplitude dynamic range, for SAS and PCIe applications it should be held Low. The Pin is defined as VODA_DB only when ENSMB is de-asserted (low). When ENSMB goes high the SMBus registers provide control of each channel, pin 4 is converted to SDA. See Table 5. |
| VODB_DB | 5 | I, 4-LEVEL, LVCMOS |
VODB_DB controls the CHB output amplitude dynamic range, for SAS and PCIe applications it should be held Low. The Pin is defined as VODB_DB only when ENSMB is de-asserted (low). When ENSMB goes high the SMBus registers provide control of each channel, pin 5 is converted to SCL. See Table 5. |
| SD_TH | 14 | I, 4-LEVEL, LVCMOS |
Controls the internal Signal Detect Threshold. This detection threshold is for system debug only and does not control the high speed datapath. See Table 3. |
| VOD_SEL | 17 | I, 4-LEVEL, LVCMOS |
VOD_SEL controls the low frequency ratio of input voltage to output voltage amplitude. See Table 5. |
| RXDET | 18 | I, 4-LEVEL, LVCMOS |
The RXDET Pin controls the receiver detect function. Depending on the input level, a 50 Ω or > 50 kΩ termination to the power rail is enabled. In a SAS/SATA system RXDET should be set to a Logic "1" state to keep the termination always enabled. The RXDET pin only controls the RXDET function in PIN MODE. PCIe applications which require SMBus Mode functionality must utilize a specific register write sequence documented in PCIe Applications . If this sequence is not utilized, SMBus configuration modes will default the input terminations to active (50 Ω). See Table 2 . |
| CONTROL PINS — BOTH PIN AND SMBus MODES (LVCMOS) | |||
| RES | 13 | I, 4-LEVEL, LVCMOS |
Reserved: This input must be left Floating. |
| VDD_SEL | 16 | I, FLOAT | Controls the internal regulator Float = 2.5 V mode Tie GND = 3.3 V mode |
| PWDN | 6 | I, LVCMOS | Tie High = Low power - power down Tie GND = Normal Operation See Table 2. |
| POWER (See Figure 11) | |||
| VIN | 15 | Power | In 3.3 V mode, feed 3.3 V to VIN In 2.5 V mode, leave floating. |
| VDD | 21, 22 | Power | Power supply pins CML/analog 2.5 V mode, connect to 2.5 V 3.3 V mode, decouple each VDD pin with 0.22 µF cap to GND |
| GND | DAP | Power | Ground pad (DAP - die attach pad). |
7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)| MIN | MAX | UNIT | ||
|---|---|---|---|---|
| Supply Voltage (VDD - 2.5 V) | -0.5 | +2.75 | V | |
| Supply Voltage (VIN - 3.3 V) | -0.5 | +4.0 | V | |
| LVCMOS Input/Output Voltage | -0.5 | +4.0 | V | |
| CML Input Voltage | -0.5 | VDD + 0.5 | V | |
| CML Input Current | -30 | +30 | mA | |
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
7.2 Handling Ratings
| MIN | MAX | UNIT | |||
|---|---|---|---|---|---|
| Tstg | Storage temperature range | -40 | 125 | °C | |
| Tsolder | Lead Temperature Range Soldering (4 sec.)(1) | 260 | °C | ||
| V(ESD) | Electrostatic discharge | Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins(2) | -5000 | 5000 | V |
| Charged device model (CDM), per JEDEC specification JESD22-C101, all pins(3) | -1250 | 1250 | |||
(1) For soldering specifications: See application note SNOA549.
(2) JEDEC document JEP155 states that 500 V HBM allows safe manufacturing with a standard ESD control process.
(3) JEDEC document JEP157 states that 250 V CDM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)| MIN | NOM | MAX | UNIT | |
|---|---|---|---|---|
| Supply Voltage (2.5 V mode) | 2.375 | 2.5 | 2.625 | V |
| Supply Voltage (3.3 V mode) | 3.0 | 3.3 | 3.6 | V |
| Ambient Temperature | -40 | 25 | +85 | °C |
| SMBus (SDA, SCL) | 3.6 | V | ||
| Supply Noise up to 50 MHz(2) | 100 | mVp-p |
7.4 Thermal Information
| THERMAL METRIC(1) | DS125BR111 | UNIT | |
|---|---|---|---|
| RTW | |||
| 24 PINS | |||
| RθJA | Junction-to-ambient thermal resistance | 35.0 | °C/W |
| RθJC(top) | Junction-to-case (top) thermal resistance | 34.0 | |
| RθJB | Junction-to-board thermal resistance | 13.4 | |
| ψJT | Junction-to-top characterization parameter | 0.3 | |
| ψJB | Junction-to-board characterization parameter | 13.4 | |
| RθJC(bot) | Junction-to-case (bottom) thermal resistance | 3.3 | |
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
7.5 Electrical Characteristics
over operating free-air temperature range (unless otherwise noted)| PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
|---|---|---|---|---|---|---|
| POWER | ||||||
| IDD | Current Consumption | VODx_DB = 0, EQ = 0, VOD_SEL = 1, RXDET = 1, PWDN = 0 VIN = 2.625 or 3.6 V |
40 | 60 | mA | |
| Power Down Current Consumption | PWDN = 1 | 7 | 13 | mA | ||
| VDD | Integrated LDO Regulator | VIN = 3.0 - 3.6 V | 2.375 | 2.5 | 2.625 | V |
| LVCMOS / LVTTL DC SPECIFICATIONS | ||||||
| Vih25 | High Level Input Voltage | 2.5 V Supply Mode | 1.7 | VDD | V | |
| Vih33 | High Level Input Voltage | 3.3 V Supply Mode | 1.7 | VIN | V | |
| Vil | Low Level Input Voltage | 0 | 0.7 | V | ||
| Voh | High Level Output Voltage (DONE pin) |
Ioh = −4 mA | 2.0 | V | ||
| Vol | Low Level Output Voltage (DONE pin) |
Iol = 4 mA | 0.4 | V | ||
| Iih | Input High Current (PWDN pin) | VIN = 3.6 V, LVCMOS = 3.6 V |
-15 | +15 | µA | |
| Iil | Input Low Current (PWDN pin) | VIN = 3.6 V, LVCMOS = 0 V |
-15 | +15 | µA | |
| 4-LEVEL INPUT DC SPECIFICATIONS | ||||||
| Iih | Input High Current with internal resistors (4–level input pin) |
VIN = 3.6 V, LVCMOS = 3.6 V |
+20 | +80 | µA | |
| Iil | Input Low Current with internal resistors (4–level input pin) |
VIN = 3.6 V, LVCMOS = 0 V |
-160 | -40 | µA | |
| Vth | Threshold 0 / R | VDD = 2.5 V (2.5 V supply mode) Internal LDO Disabled See Table 1 for details |
0.40 | V | ||
| Threshold R / Float | 1.25 | |||||
| Threshold Float / 1 | 2.1 | |||||
| Threshold 0 / R | VIN = 3.3 V (3.3 V supply mode) Internal LDO Enabled See Table 1 for details. |
0.55 | V | |||
| Threshold R / Float | 1.65 | |||||
| Threshold Float / 1 | 2.7 | |||||
| CML RECEIVER INPUTS (IN_n+, IN_n-) | ||||||
| RLRX-diff | RX Differential return loss | SDD11 10 MHz | -19 | dB | ||
| SDD11 2 GHz | -14 | |||||
| SDD11 6-11.1 GHz | -8 | |||||
| RLRX-cm | RX Common mode return loss | 0.05 - 5 GHz | -10 | dB | ||
| ZRX-dc | RX DC common mode impedance | Tested at VDD = 2.5 V | 40 | 50 | 60 | Ω |
| ZRX-diff-dc | RX DC differential mode impedance | Tested at VDD = 2.5 V | 80 | 100 | 120 | Ω |
| VRX-signal-det-diff-pp | Signal detect assert level | SD_TH = F (float), 0101 pattern at 12 Gbps |
50 | mVp-p | ||
| VRX-idle-det-diff-pp | Signal detect de-assert level | SD_TH = F (float), 0101 pattern at 12 Gbps |
37 | mVp-p | ||
| HIGH SPEED OUTPUTS | ||||||
| TTX-RISE-FALL | Transmitter rise/fall time (3) | 20% to 80% of differential output voltage | 40 | ps | ||
| TRF-MISMATCH | Transmitter rise/fall mismatch (4) | 20% to 80% of differential output voltage | 0.01 | UI | ||
| RLTX-DIFF | TX Differential return loss | SDD22 10 MHz - 2 GHz | -15 | dB | ||
| SDD22 5.5 GHz | -12 | |||||
| SDD22 11.1 GHz | -10 | dB | ||||
| RLTX-CM | TX Common mode return loss | 0.05 - 5 GHz | -10 | dB | ||
| ZTX-DIFF-DC | DC differential TX impedance | 100 | Ω | |||
| ITX-SHORT | Transmitter short circuit current limit | Total current, output shorted to VDD or GND | 20 | mA | ||
| VTX-CM-DC-ACTIVE-IDLE-DELTA | Absolute delta of DC common mode voltage during L0 and electrical idle | 100 | mV | |||
| VTX-CM-DC-LINE-DELTA | Absolute delta of DC common mode voltage between TX+ and TX- | 25 | mV | |||
| HIGH SPEED OUTPUTS | ||||||
| VTX-diff1-pp | Output Voltage Differential Swing | Differential measurement with OUTx+ and OUTx-, AC-Coupled and terminated by 50 Ω to GND, Inputs AC-Coupled, VODx_DB = 0 dB, VID = 600 mVp-p VOD = 001'b (0.7*VID) |
440 | 500 | 550 | mVp-p |
| VTX-diff2-pp | Output Voltage Differential Swing | Differential measurement with OUTx+ and OUTx-, AC-Coupled and terminated by 50 Ω to GND, Inputs AC-Coupled, VODx_DB = 0 dB, VID = 1000 mVp-p VOD = 001'b (0.7*VID) (5) |
630 | 700 | 740 | mVp-p |
| VTX-diff3-pp | Output Voltage Differential Swing | Differential measurement with OUTx+ and OUTx-, AC-Coupled and terminated by 50 Ω to GND, Inputs AC-Coupled, VODx_DB = 0 dB, VID = 600 mVp-p VOD = 111'b (1.05*VID) (5) |
570 | 650 | 740 | mVp-p |
| VTX-diff4-pp | Output Voltage Differential Swing | Differential measurement with OUTx+ and OUTx-, AC-Coupled and terminated by 50 Ω to GND, Inputs AC-Coupled, VODx_DB = 0 dB, VID = 1000 mVp-p VOD = 111'b (1.05*VID) (5) |
800 | 1010 | 1215 | mVp-p |
| TTX-IDLE-DATA | Time to transition to valid differential signal after idle | VID = 1.0 Vp-p, 3 Gbps | 0.04 | ns | ||
| TTX-DATA-IDLE | Time to transition to idle after differential signal | VID = 1.0 Vp-p, 3 Gbps | 0.70 | ns | ||
| TPD | Differential Propagation Delay | EQ = Level 1 to Level 4 | 70 | ps | ||
| EQUALIZATION | ||||||
| DJE1 | Residual Deterministic Jitter at 6 Gbps | Input: 5” Differential Stripline, 5mil trace width, FR4, VID = 0.8 Vp-p, PRBS15, EQ = 0x01, VOD = 111'b, VODx_DB = 0 dB |
0.06 | UI | ||
| DJE2 | Residual Deterministic Jitter at 12 Gbps | Input: 5” Differential Stripline, 5mil trace width, FR4, VID = 0.8 Vp-p, PRBS15, EQ = 0x01, VOD = 111'b, VODx_DB = 0 dB |
0.12 | UI | ||
| RJADD1 | Additive Random Jitter (1) | Evaluation Module (EVM) only, FR4, VID = 0.8 Vp-p, PRBS7, EQ = 0x00, VOD = 111'b, VODx_DB = 0 dB |
< 300 | fs RMS | ||
| RJADD2 | Additive Random Jitter (1) | Input: 10" Differential Stripline, 5 mil trace width, FR4, VID = 0.8 Vp-p, PRBS7, EQ = 0x03, VOD = 111'b, VODx_DB = 0 dB |
< 400 | fs RMS | ||
(1) Additive random jitter is given in RMS value by the following equation: RJADD = √[(Output Jitter)2 - (Input Jitter)2] . The typical source input jitter for these measurements is 150 fs RMS.
(2) Allowed supply noise (mVp-p sine wave) under typical conditions.
(3) Rise / Fall time measurements will vary based on EQ setting, Input Amplitude, and input edge rate.
(4) Mismatch between rise time and fall time for a given channel.
(5) The output VOD level is not fixed. It will be adjusted automatically based on the VID input amplitude level and the frequency content. The DS125BR111 repeater is designed to be transparent, so the TX-FIR (de-emphasis) is passed to the RX to support handshake negotiation link training.
7.6 Electrical Characteristics — Serial Management Bus Interface
Over recommended operating supply and temperature ranges unless other specified.| PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
|---|---|---|---|---|---|---|
| SERIAL BUS INTERFACE DC SPECIFICATIONS | ||||||
| VIL | Data, Clock Input Low Voltage | 0.8 | V | |||
| VIH | Data, Clock Input High Voltage | 2.1 | 3.6 | V | ||
| VOL | Output Low Voltage | SDA or SCL, IOL = 1.25 mA | 0 | 0.36 | V | |
| VDD | Nominal Bus Voltage | 2.375 | 3.6 | V | ||
| IIH-pin | Input Leakage Per Device pin | +20 | +150 | µA | ||
| IIL-pin | Input Leakage Per Device pin | -160 | -40 | µA | ||
| CI | Capacitance for SDA and SCL | See(1)(2) | < 5 | pF | ||
| RTERM | External Termination Resistance pull to VDD = 2.5 V ± 5% OR 3.3 V ± 10% | Pullup VDD = 3.3 V(1)(2)(3) | 2000 | Ω | ||
| Pullup VDD = 2.5 V(1)(2)(3) | 1000 | Ω | ||||
(1) Typical value.
(2) Recommended maximum capacitance load per bus segment is 400 pF.
(3) Maximum termination voltage should be identical to the device supply voltage.
7.7 Timing Requirements
| PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
|---|---|---|---|---|---|---|
| SERIAL BUS INTERFACE TIMING SPECIFICATIONS | ||||||
| FSMB | Bus Operating Frequency | ENSMB = VDD (Slave Mode) | 400 | kHz | ||
| ENSMB = FLOAT (Master Mode) (1) | 280 | 400 | 520 | kHz | ||
| tFALL | SCL or SDA Fall Time | Read operation RPU = 4.7 kΩ, Cb < 50 pF |
60 | ns | ||
| tRISE | SCL or SDA Rise Time | Read operation RPU = 4.7 kΩ, Cb < 50 pF |
140 | ns | ||
| tF | Clock/Data Fall Time | See(2) | 300 | ns | ||
| tR | Clock/Data Rise Time | See(2) | 1000 | ns | ||
(1) The external EEPROM device address byte must be 0xA0 and capable of 1 MHz operation at 2.5 V and 3.3 V.
(2) Compliant to SMBus 2.0 physical layer specification. See System Management Bus (SMBus) Specification Version 2.0, section 3.1.1 SMBus common AC specifications for details.
Figure 1. Output Rise And Fall Transition Time
Figure 2. Propagation Delay Timing Diagram
Figure 3. Transmit Idle-Data and Data-Idle Response Time
Figure 4. SMBus Timing Parameters
7.8 Typical Characteristics
| Test Conditions | ||
| Data Rate/Test Pattern: | 1.5625 Gbps / 101010 Repeating Pattern |
|
| VOD: | Level 6 | |
| EQ: | Level 1 | |
| VOD_DB: | 000'b | |
| VDD: | 2.5 V | |
| Test Conditions | ||
| Data Rate/Test Pattern: | 1.5625 Gbps / 101010 Repeating Pattern | |
| EQ: | Minimum | |
| VOD_DB: | 000'b | |
| Temperature: | 25°C | |
| VDD: | 2.5 V | |
| Test Conditions | ||
| Data Rate/Test Pattern: | 1.5625 Gbps / 101010 Repeating Pattern |
|
| VOD: | Level 6 | |
| EQ: | Level 1 | |
| VOD_DB: | 000'b | |
| Temperature: | 25°C | |
