DS110DF1610 8.5- to 11.3-Gbps 16-Channel Retimer

6.3.1.1 AC-Coupled Receiver With Signal Detect

The differential receiver for each DS110DF1610 channel contains on chip AC coupling capacitors. The minimum bandwidth for this AC coupled receiver is 16kHz. The receiver also contains a signal detect circuit.

The signal detect circuit monitors the energy level on the receiver inputs and powers on or off the rest of the high speed data path if a signal is detected or not. By default, each channel allows the signal detect circuit to automatically power on or off the rest of the high speed data path depending on if a signal is present. Users can obtain manual control over the signal detect block through the SMBus channel registers. This can be useful if it is desired manually force channels to be disabled. For information on how to manually operate the signal detect circuit please see the DS110DF1610 Programming Guide and channel register 0x15 information.

6.3.1.2 CTLE

The CTLE in the DS110DF1610 is a fully adaptive equalizer with adjustable bandwidth and optional limiting stage. The CTLE is adapted to a boost setting according to a Figure of Merit (FOM) during the lock acquisition process. Once the CDR has locked, the CTLE boost level will be frozen until a manual re-adapt command is issued or until the CDR re-enters the lock acquisition state.

The CTLE consists of 4 stages, with each stage having 2-bit boost control. This allows for 256 different stage-boost combinations. The CTLE adaption algorithm allows the CTLE to adapt through 32 of these stage-boost combinations. These 32 stage-boost combinations comprise the EQ Table in the channel registers; see channel registers 0x40 through 0x5F. This EQ Table can be reprogrammed to support up to 32 of the 256 stage-boost settings. Users also have the option of limiting the EQ table length to any value between a minimum value of 1 and a maximum value of 32.

CTLE boost levels are determined by summing the boosts levels of the 4 stages. Different stage-boost combinations that sum to the same number will have approximately the same boost level, but will result in a different shape for the EQ transfer function (boost curve). The boost levels can be set between 6 dB and 38 dB.

The CTLE bandwidth can be adjusted through SMBus control to 3 different levels:

The fourth stage in the CTLE can be programmed through the SMBus interface to become a limiting stage rather than a linear stage. This is useful in some applications, but it should not be typically used in combination with the DFE.

6.3.1.3 Cross Point Switch

Each quad has a 4x4 non-blocking analog cross point switch. This allows for full switching or broadcasting of data between any input within the quad to any output within the quad. Since the cross point switch is an analog implementation, all of the channels are allowed to operate asynchronously. The analog implementation also minimizes added latency through the device.

As shown in Figure 1, the cross point switch connections for each quad are located between CTLE and DFE in each channel.

The cross point switch consists of consists of 4 sets of MUXs and buffers. In each channel there is a local buffer and a multi-drive buffer. The local buffer transmits data from the CTLE to the DFE of the same channel. The multi drive buffer transmits data from the CTLE to the DFE(s) of other channels within the quad. Each channel has two MUXs:

1. Data path mux – Selects whether to get data from the local buffer or from other channel’s multi-driver buffer
2. Control bus mux – Selects where the signal detect and EQ control bus should be connected. This setting should mirror the data path mux setting. Note, when an EQ is connected to another channel’s CDR the EQ becomes associated with that CDR’s register set. For example, if the cross point was configured to do point to point switching from the inputs of channel 0 to the output of channel 1 and the inputs of channel 1 to the outputs of channel 0, the EQ physically located at the pins for inputs of channel 0 would be accessible through the register set of channel 1.

A simplified diagram of the cross point switch is shown in Figure 3.

Figure 3. Cross Point Switch Diagram

In a typical point-to-point switching application users must configure the following for each channel:

1. Control bus mux setting (ch reg 0x9B)
2. Data path mux setting (ch reg 0x96)
3. Enabling/Disabling the local or multi-drive buffers for each channel (ch reg 0x96)
4. Cross point enable bit (ch reg 0x96)
5. Perform a CDR reset and reset release (ch reg 0x0A)

Note, when using the cross point switch the local and multi-drive buffer should both be enabled regardless of the desired configuration.

The cross point switch can also be used to replicate data or perform a broadcast function. The options for this type of configuration include:

• 1:2 – any channel input to any 2 channels output
• 1:3 – any channel input to any 3 channels output
• 1:4 – any channel input to all 4 channels output

When the cross point switch is configured to replicate/broadcast data a master must be assigned during the cross point configuration. The master channel will have control over the CTLE adaption. All of the slave channels will be able to adapt their own DFE, but will not have control to adapt the CTLE. In this type of configuration there must be 1 channel assigned as a master. All other channels in the broadcast network must be assigned as slaves. There cannot be more than one master channel in a broadcast network.

In a typical data replication/broadcast application users must configure the following for each channel:

1. Control bus mux setting (ch reg 0x9B)
2. Data path mux setting (ch reg 0x96)
3. Enabling/Disabling the local or multi-drive buffers for each channel (ch reg 0x96)
4. Master/Slave assignment (ch reg 0x96)
5. Cross point enable bit (ch reg 0x96)
6. Perform a CDR reset and reset release (ch reg 0x0A)

6.3.1.4 DFE With VGA

A 5-tap DFE with a VGA can be enabled within the data path of each channel to assist with reducing the effects of cross talk, reflections, or post cursor inter-symbol interference (ISI). The DFE must be manually enabled, regardless of the selected adapt mode. Once the DFE has been enabled it can be configured to adapt only during lock acquisition or to adapt continuously. The DFE can also be manually configured to specified tap polarities and tap weights. However, when the DFE is configured manually the DFE auto-adaption should be disabled.

The DFE taps are all feedback taps with 1UI spacing. Each tap has a specified boost weight range and polarity bit.

A VGA is located at the input to the DFE block. The VGA has 2-bit control to allow for 4 levels of boost. The VGA can be used to assist in the recovery of extremely small signals. Note that the VGA is integrated within the DFE, so in order to use the VGA the DFE must be enabled.

6.3.1.5 Clock and Data Recovery

The CDR block consists of a Phase Locked Loop (PLL), reference clock based PPM counter, Input and Output Data Multiplexers (mux) and circuits to monitor single bit transitions and detect false locking. The CDR sampling position is fixed at the 0.5UI location for each bit.

By default, the equalized data is fed into the CDR for clock and data recovery. This data is then output to FIR filter and differential driver. Users can configure the CDR data to route the recovered clock and data to the PRBS checker. Users also have the option of configuring the output of the CDR to send raw non-retimed data, or data from the pattern generator.

The CDR requires the following in order to be properly configured:

• Input reference clock with proper reference clock divider setting to run the PPM counter.
• Expected data rates must be programmed into the CDR either through the rate/sub-rate table or entered manually with the corrected divider settings.

6.3.1.6 Reference Clock

The reference clock is not part of the CDR’s PLL. The reference clock is connected only to the PPM counter for each CDR. The PPM counter constrains the allowable lock ranges of the CDR according to the programmed values in the rate/sub-rate table or the manually entered data rates.

The reference clock can be set to any of the 3 allowable frequencies independant of the data rate of the high speed channel. The input reference clock can be single-ended or differential for the 25 MHz or 125 MHz settings. If the 312.5 MHz setting is used, the input signaling type should be differential. The reference clock can be output through the CLK_MON pins for observation or daisy chaining the reference clock to the next device. If the CLK_MON port is used for daisy chaining then the output frequency should be set to 25 MHz.

If the reference clock port is configured to operate in single-ended mode, the 2.5V LVCMOS clock signal should be applied to the REF_CLK_P pin. In this configuration the REF_CLK_N pin should be floated (N/C). In this case the LVCMOS clock signal should be DC coupled into the REF_CLK_P pin.

Configuring the reference clock frequency is done in share register 0x02[6:5]. Configuring the reference clock input port for single-ended or differential mode operation is done in share register 0x0B[4]. Enabling or disabling the CLK_MON port is done in share reg 0x0A[0]. Selecting the divided (25 MHz) or undivided (input frequency) is done in share register 0x04[7].

6.3.1.7 Differential Driver With FIR Filter

The DS110DF1610 output driver can be manually powered off through SMBus register control. The outputs of the DS110DF1610 also have optional output termination resistors that can be enabled when the driver is manually powered down. These termination resistors can help reduce the effects of cross talk in high speed systems.

The DS110DF1610 uses a 3-tap FIR filter to assist with transmit equalization. The FIR filter consists of a pre cursor tap, a main cursor tap and a post cursor tap. Each tap has a polarity bit and 64 available levels. By default, the main cursor tap is set to a positive polarity, while the pre cursor and post cursor taps are set to a negative polarity. Users can invert the polarity of all 3 FIR taps to invert the polarity of the output data.

6.3.2.1 Pattern Generator

Each channel in the DS110DF1610 can be configured to generate a 16-bit user defined data pattern or a pseudo random bit sequence (PRBS). The user defined pattern can also be set to automatically invert every other 16-bit symbol for DC balancing purposes. The DS110DF1610 pattern generator supports the following PRBS sequences:

• PRBS – 7
• PRBS – 9
• PRBS – 15
• PRBS – 31

6.3.2.2 Pattern Checker

The pattern checker can be manually set to lock for specific PRBS sequences and polarities or it can be set to automatically detect the incoming pattern and polarity. If the pattern checker is meant to work with a user defined pattern, then it must be programmed to search for that exact pattern.

The pattern checker consists of a 47-bit bit counter and an 11-bit error counter. In order to read out the bit and error counters, the pattern checker must first be frozen. Continuous operation with simultaneous read out of the bit and error counters is not possible in this implementation.

6.3.2.3 Eye Opening Monitor

The DS110DF1610’s Eye Opening Monitor (EOM) can be used for 2 functions:

1. Horizontal Eye Opening (HEO) and Vertical Eye Opening (VEO) measurement
2. Full Eye Diagram Capture

The HEO measurement is made at the 0V crossing and is read in channel register 0x27. The VEO measurement is made at the 0.5 UI mark and is read in channel register 0x28. The HEO and VEO registers can be read from channel registers 0x27 and 0x28 at any time while the CDR is locked. The following equations are used to convert the contents of channel registers 0x27 and 0x28 into their appropriate units:

• HEO [UI] = ch reg 0x27 ÷ 64
• VEO [mV] = ch reg 0x28 x 3.125

A full eye diagram capture can be performed when the CDR is locked. The eye diagram is constructed within a 64 x 64 array, where each cell in the matrix consists of an 16-bit word. Users can manually adjust the vertical scaling of the EOM or allow the state machine to control the scaling which is the default option. The horizontal scaling controlled by the state machine and is always directly proportional to the data rate.

When a full eye diagram plot is captured, the retimer will shift out 4 16-bit words of junk data that should be discarded followed by 4096 16-bit words that make up the 64 x 64 eye plot. The first actual word of the eye plot from the retimer is for (X, Y) position (0,0). Each time the eye plot data is read out the voltage position is incremented. Once the voltage position has incremented to position 63, the next read will cause the voltage position to reset to 0 and the phase position to increment. This process will continue until the entire 64 x 64 matrix is read out. Figure 4 shows the EOM read out sequence overlaid on top of a simple eye opening plot. In this plot any hits are shown in green. This type of plot is helpful for quickly visualizing the HEO and VEO. Users can apply different algorithms to the output data to plot density or color gradients to the output data.

Figure 4. EOM Full Eye Capture Readout

To manually control the EOM vertical range, remove scaling control from the state machine then select the desired range:

1. Channel Reg 0x2C[6] → 0
2. See table:

CH REG 0x11[7:6] VALUE	EOM VERTICAL RANGE [mV]
2’b00	±100
2'b01	±200
2'b10	±300
2'b11	±400

The EOM operates as an under-sampled circuit. This allows the EOM to be useful in identifying over equalization, ringing and other gross signal conditioning issues. However, the EOM cannot be correlated to a bit error rate.

The EOM can be accessed in two ways to read out the entire eye plot:

• Multi-byte reads can be used such that data is repeatedly latched out from channel register 0x25.
• Or single byte reads. With single byte reads, the MSB are located in register 0x25 and the LSB are located in register 0x26. In this mode, the device must be addressed each time a new byte is read.

To perform a full eye capture with the EOM, follow these steps within the desired channel register set:

6.3.2.4 Interrupt Signals

The DS110DF1610 can be configured to report different events as interrupt signals. These interrupt signals do not impact the operation of the device, but merely report that the selected event has occurred. The interrupt bits in the register sets are all sticky bits. This means that when an event triggers an interrupt the status bit for that interrupt is set to logic HIGH. This interrupt status bit will remain at logic HIGH until the bit has been read. Once the bit has been read it will be automatically cleared, which allows for new interrupts to be detected. The DS110DF1610 will report the occurrence of an interrupt through the INTERR_IO pin. The INTERR_IO pin is an open drain output that will pull the line low when an interrupt signal is triggered.

Note that all available interrupts are disabled by default. Users must activate the various interrupts before they can be used.

The interrupts available in the DS110DF1610 are:

• CDR loss of lock
• CDR locked
• Signal detect loss
• Signal detected
• PRBS pattern generator lock up
• PRBS pattern checker bit error detected
• HEO/VEO threshold violation

When an interrupt occurs, share register 0x08 and 0x09 report which channel generated the interrupt request. Users can then select the channel(s) that generated the interrupt request and service the interrupt by reading the appropriate interrupt status bits in the corresponding channel registers.

6.3.3.1 Lock Sequencer

A channel will temporarily consume a higher amount of power while its CDR is attempting to lock, compared to when the CDR is locked. In order to reduce the impact of a power consumption spike when data is transmitted to a DS110DF1610, the internal lock sequencer will limit the number of active channels that are simultaneously allowed to attempt to lock.

The lock sequencer grants tokens to various channels that have detected a signal at the input to the CTLE. Once a channel has achieved CDR lock, it returns its token to the lock sequencer. The lock sequencer will distribute any available tokens on a first come first serve basis to any channel that is allowed to attempt lock and that has detected a valid signal.

The lock sequencer is configurable in the share registers. Users can control which channels are allowed to attempt lock when a signal is present by configuring share registers 0x0F and 0x10. Users can also limit the number of channels that are allowed to simultaneously attempt to lock by configuring share register 0x05.

RESET_IO Pin

The RESET_IO pin in the DS110DF1610 emulates a power on reset (POR). This type of reset re-initializes the entire device including the SMBus address strap settings and restores both share and channel register defaults.

The RESET_IO pin triggers a reset on the rising edge of the signal. It is not recommended to hold the RESET_IO pin at a logic LOW state for an extended period of time. RESET_IO should be held at logic HIGH during power on. After power on, the RESET_IO pin should be pulsed low for a minimum of 10 µs to perform a reset.

6.4.1.1 SDA and SDC

In both SMBus master and SMBus slave mode, the DS110DF1610 is configured using the SMBus. The SMBus consists of two lines, the SDA or serial data line and the SCL or serial clock line. In the DS110DF1610 these pins are 3.3V tolerant. The SDA and SCL lines are both open-drain. They require a pull-up resistor to a supply voltage, which may be either 2.5V or 3.3V. A pull-up resistor in the 2KΩ to 5KΩ range will provide reliable SMBus operation.

6.4.1.2 Address Line

In either SMBus mode the DS110DF1610 must be assigned an SMBus address. A unique address should be assigned to each device on the SMBus.

The DS110DF1610 can be configured to respond to one of the sixteen SMBus addresses listed in the table below. GPIO1 and GPIO0 are configured to be four level inputs immediately after the device powers on. Logic 0 can be set by tying the pin to ground through a ≤1kΩ resistor. Logic R is set by tying the pin to ground through a 20kΩ resistor. Logic F is set by floating the pin. Logic 1 is set by tying the pin to VCC = 2.5V through a ≤1kΩ resistor.

When an SMBus device is addressed for reading or writing a bit is appended to the address a the least significant bit space. This bit is set to 0 for a write or to 1 for a read.

6.4.1.3 Device Configuration in SMBus Slave Mode

The configurable settings of the DS110DF1610 may be set independently for each channel at any time after power up using the SMBus. A register write is accomplished when the controller sends a START condition on the SMBus followed by the Write address of the DS110DF1610 to be configured. After sending the Write address of the DS110DF1610, the controller sends the register address byte followed by the register data byte. The DS110DF1610 acknowledges each byte written to the controller according to the data link protocol of the SMBus Version 2.0 Specification. See this specification for additional information on the operation of the SMBus.

There are 3 types of device registers in the DS110DF1610. These are the global registers, shared registers and the channel registers. The global registers are programmed to access the various channel registers or the shared registers. The shared registers control or allow observation of settings which affect the operation of all channels of the DS110DF1610 at the greater device level.

The channel registers are used to set all the configuration settings of the DS110DF1610. They provide independent control for each channel of the DS110DF1610 for all the settable device characteristics. Any registers not described in the tables that follow should be treated as reserved. The user should not try to write new values to these registers. The user-accessible registers described in the tables that follow provide a complete capability for customizing the operation of the DS110DF1610 on a channel-by-channel basis.

Table 2. Shared Registers

Table 3. Channel Registers, 0 to 1F

Table 4. Channel Registers, 20 to 39

Table 5. Channel Registers, 3A to 59

Table 6. Channel Registers, 5A to 9B