SNLS493A October   2014  – January 2015 DS80PCI810

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Handling Ratings
    4. 6.4 Recommended Operating Conditions
    5. 6.5 Thermal Information
    6. 6.6 Electrical Characteristics
    7. 6.7 Electrical Characteristics — Serial Management Bus Interface
    8. 6.8 Timing Requirements Serial Bus Interface
    9. 6.9 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
      1. 7.2.1 19
      2. 7.2.2 Functional Datapath Blocks
    3. 7.3 Feature Description
      1. 7.3.1 Typical 4-Level Input Thresholds
    4. 7.4 Device Functional Modes
      1. 7.4.1 Pin Control Mode:
      2. 7.4.2 Slave SMBus Mode:
      3. 7.4.3 SMBus Master Mode
      4. 7.4.4 Signal Conditioning Settings
    5. 7.5 Programming
      1. 7.5.1 EEPROM Address Map for Single Device
      2. 7.5.2 SMBus
      3. 7.5.3 Transfer Of Data Via The SMBus
      4. 7.5.4 SMBus Transactions
    6. 7.6 Writing a Register
    7. 7.7 Reading a Register
    8. 7.8 Register Maps
  8. 8 Applications and Implementation
    1. 8.1 Application Information
      1. 8.1.1 DS80PCI810 versus DS80PCI800
      2. 8.1.2 Signal Integrity in PCIe Applications
      3. 8.1.3 Rx Detect Functionality in PCIe Applications
    2. 8.2 Typical Applications
      1. 8.2.1 Generic High Speed Repeater
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
        3. 8.2.1.3 Application Performance Plots
          1. 8.2.1.3.1 Pre-Channel Only Setup
          2. 8.2.1.3.2 Pre-Channel and Post-Channel Setup
      2. 8.2.2 PCIe Board Applications (PCIe Gen-3)
        1. 8.2.2.1 Design Requirements
        2. 8.2.2.2 Design Procedure
        3. 8.2.2.3 Application Performance Plots
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Trademarks
    2. 11.2 Electrostatic Discharge Caution
    3. 11.3 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

4 Revision History

Changes from * Revision (September 2014) to A Revision

  • Changed pin assignment numbers for OUTB_2+/- and OUTB_3+/- to correct typo Go
  • Changed ENSMB pin type to 4-level LVCMOS per input pin behaviorGo
  • Changed Handling Ratings table to ESD Ratings table. Moved Tstg and Tsolder parameters into Absolute Maximum Ratings table.Go
  • Changed register map rows to combine multiple consecutive registers with a value of all zeros and no EEPROM-relevant bits Go