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  • DP83825I Low Power 10/100 Mbps Ethernet Physical Layer Transceiver

    • SNLS638B December   2018  – January 2025

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  • DP83825I Low Power 10/100 Mbps Ethernet Physical Layer Transceiver
  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
    1.     DP83825I Pin Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Requirements
    7. 5.7 Timing Diagrams
    8. 5.8 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1  Auto-Negotiation (Speed / Duplex Selection)
      2. 6.3.2  Auto-MDIX Resolution
      3. 6.3.3  Energy Efficient Ethernet
        1. 6.3.3.1 EEE Overview
        2. 6.3.3.2 EEE Negotiation
      4. 6.3.4  EEE for Legacy MACs Not Supporting 802.3az
      5. 6.3.5  Wake-on-LAN Packet Detection
        1. 6.3.5.1 Magic Packet Structure
        2. 6.3.5.2 Magic Packet Example
        3. 6.3.5.3 Wake-on-LAN Configuration and Status
      6. 6.3.6  Low Power Modes
        1. 6.3.6.1 Active Sleep
      7. 6.3.7  IEEE Power Down
      8. 6.3.8  Deep Power Down
      9. 6.3.9  Reduced Media Independent Interface (RMII)
      10. 6.3.10 RMII Repeater Mode
      11. 6.3.11 Serial Management Interface
        1. 6.3.11.1 Extended Register Space Access
        2. 6.3.11.2 Read Operation
        3. 6.3.11.3 Write Operation
      12. 6.3.12 100BASE-TX
        1. 6.3.12.1 100BASE-TX Transmitter
          1. 6.3.12.1.1 Code-Group Encoding and Injection
          2. 6.3.12.1.2 Scrambler
          3. 6.3.12.1.3 NRZ to NRZI Encoder
          4. 6.3.12.1.4 Binary to MLT-3 Converter
        2. 6.3.12.2 100BASE-TX Receiver
      13. 6.3.13 10BASE-Te
        1. 6.3.13.1 Squelch
        2. 6.3.13.2 Normal Link Pulse Detection and Generation
        3. 6.3.13.3 Jabber
        4. 6.3.13.4 Active Link Polarity Detection and Correction
      14. 6.3.14 Loopback Modes
        1. 6.3.14.1 MII Loopback
        2. 6.3.14.2 PCS Loopback
        3. 6.3.14.3 Digital Loopback
        4. 6.3.14.4 Analog Loopback
        5. 6.3.14.5 Reverse Loopback
      15. 6.3.15 BIST Configurations
      16. 6.3.16 Cable Diagnostics
        1. 6.3.16.1 TDR
        2. 6.3.16.2 Fast Link-Drop Functionality
    4. 6.4 Device Functional Modes
    5. 6.5 Programming
      1. 6.5.1 Straps Configuration
        1. 6.5.1.1 Straps for PHY Address
    6. 6.6 Device Registers
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Applications
      1. 7.2.1 Design Requirements
        1. 7.2.1.1 Clock Requirements
          1. 7.2.1.1.1 Oscillator
          2. 7.2.1.1.2 Crystal
      2. 7.2.2 Detailed Design Procedure
        1. 7.2.2.1 RMII Layout Guidelines
        2. 7.2.2.2 MDI Layout Guidelines
        3. 7.2.2.3 TPI Network Circuit
        4. 7.2.2.4 VOD Configuration
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
        1. 7.4.1.1 Signal Traces
        2. 7.4.1.2 Return Path
        3. 7.4.1.3 Transformer Layout
          1. 7.4.1.3.1 Transformer Recommendations
        4. 7.4.1.4 Capacitive DC Blocking
        5. 7.4.1.5 Metal Pour
        6. 7.4.1.6 PCB Layer Stacking
      2. 7.4.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Receiving Notification of Documentation Updates
    2. 8.2 Support Resources
    3. 8.3 Trademarks
    4. 8.4 Electrostatic Discharge Caution
    5. 8.5 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information
  12. IMPORTANT NOTICE
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Data Sheet

DP83825I Low Power 10/100 Mbps Ethernet Physical Layer Transceiver

1 Features

  • Ultra Small Form Factor 10/100Mbps PHY : QFN 3mm × 3mm, 24 pin
  • Cable reach up to 150 meters
  • Very low power consumption < 127mW
  • Integrated MDI and MAC termination resistors
  • Programmable energy saving modes
    • Active sleep
    • Deep power-down
    • Energy Efficient Ethernet (EEE) IEEE 802.3az
    • EEE support for legacy MAC
    • Wake-on-LAN (WoL)
  • Voltage mode line driver
  • MAC interface : RMII (master and slave mode)
  • Single 3.3V power supply
  • I/O voltages: 1.8V and 3.3V
  • Repeater : RMII back-to-back mode in unmanaged mode
  • MDC/MDIO Interface for configuration and status
  • Fast link drop modes
  • Diagnostics tools: cable diagnostics, built-in self test (BIST), loopback modes
  • Programmable Hardware interrupt pin
  • Operating temperature range: –40°C to 85°C
  • Compliant to IEEE 802.3 100BASE-TX and 10BASE-Te specification

2 Applications

  • Building automation: IP camera, HMI
  • Motor Drives
  • Electronic point of sale
  • Factory automation

3 Description

The DP83825I is an ultra small form factor, very low power Ethernet Physical Layer transceiver with integrated PMD sublayers to support 10BASE-Te, 100BASE-TX Ethernet protocols. The PHY supports up to 150 meters reach over CAT5e cable. The DP83825I interfaces directly to twisted pair media via an external transformer.

The DP83825I also supports Energy Efficient Ethernet, Wake-on-LAN and MAC isolation to further lower the system power consumption. Energy Efficient Mode can be enabled through register configuration for legacy MACs not supporting EEE signaling over MAC. DP83825I can operate in unmanaged repeater mode. In this mode, DP83825I works as a repeater without register configuration. The DP83825I offers integrated cable diagnostic tools, built-in self-test and loopback capabilities for ease of development and debug.

Device Family Information
PART NUMBER PACKAGE(1) BODY SIZE (NOM) (2) ATTRIBUTES
DP83826E VQFN (32) 5.00mm × 5.00mm Lowest latency, common pinout
DP83825I WQFN (24) 3.00mm × 3.00mm Small size, optimized cost
DP83822HF/IF/H/I VQFN (32) 5.00mm × 5.00mm Wide temperature range, fiber, and RGMII support
(1) For all available packages, see the orderable addendum at the end of the data sheet.
(2) The package size (length × width) is a nominal value and includes pins, where applicable.
DP83825I DP83825I Application DiagramDP83825I Application Diagram

4 Pin Configuration and Functions

DP83825I DP83825 RMQ Package24-Pin QFNTop View Figure 4-1 DP83825 RMQ Package24-Pin QFNTop View

DP83825I Pin Functions

PIN TYPE(1) DESCRIPTION
NAME NO.
TX_EN 1 Reset: I, PD
Active: I, PD		 RMII Transmit Enable: TX_EN is active high signal and is presented on the rising edge of the TX_CLK. TX_EN indicates the presence of valid data inputs on TX_D [1:0].
50MHzOut/LED2 2 Reset: I, PD, S
Active: O

RMII Master Mode: 50MHz Clock Out(default).

RMII Slave Mode: LED_2(default). This pin can be configured as GPIO using register configuration.
INTR/PWRDN 3 Reset: I, PU
Active: I/O, PU		 Interrupt / Power Down(default): The default function of this pin is power down. Register access is required to configure this pin as an interrupt. In power-down function, an active low signal on this pin places the device in power down mode. When this pin is configured as an interrupt pin, this pin is asserted low when an interrupt condition occurs. The pin has an open-drain output with a weak internal pullup (9.5kΩ). Some applications can require an external pullup resistor.
LED0 4 Reset: I, PD, S
Active: O		 LED0 : Activity Indication LED indicates transmit and receive activity in addition to the status of the Link. The LED is ON when Link is good. The LED blinks when the transmitter or receiver is active. This pin can also act as GPIO through register configuration.

This pin is at 3.3V always and not linked to voltage supplied to VDDIO pin. This is to avoid external components when operating PHY at VDDIO 1.8V.
RST_N 5 Reset: I, PU
Active: I, PU		 RST_N: This pin is an active low reset input. Asserting this pin low for at least 25μs forces a reset process to occur. Initiation of reset causes strap pins to be re-scanned and resets all the internal registers of the PHY to default value.

This pin is at 3.3V always and not linked to voltage supplied to VDDIO pin. This is to avoid external components when operating PHY at VDDIO 1.8V.
VDDA3V3 6 Power Input Analog Supply: 3.3V. For decoupling capacitor requirements, refer to the Section 7.3 section.
RD_M 7 A Differential Receive Input (PMD): These differential inputs are automatically configured to accept either 10BASE-Te, 100BASE-TX specific signaling mode
RD_P 8 A
GND 9 GND Ground: Connect to Ground
TD_M 10 A Differential Transmit Output (PMD): These differential outputs are configured to either 10BASE-Te, 100BASE-TX signaling mode based on configuration chosen for PHY.
TD_P 11 A
XO 12 A Crystal Output: Reference Clock output. XO pin is used for crystal only. This pin can be left floating when a CMOS-level oscillator is connected to XI.
XI/50MHzIn 13 A Crystal / Oscillator Input Clock

RMII Master mode: 25MHz ±50ppm-tolerance crystal or oscillator clock

RMII Slave mode: 50MHz ±50ppm-tolerance CMOS-level oscillator clock
RBIAS 14 A This pin needs a biasing resistor. Connect a 6.49kΩ ±1% tolerance resistor between RBIAS pin and ground.
MDIO 15 Reset: I, PU-10kΩ
Active: I/O, PU-10kΩ		 Management Data I/O: Bidirectional management data signal that can be source by the management station or the PHY. This pin has internal pullup of 10kΩ. External pullup of up to 2.2kΩ can be added if needed
MDC 16 Reset: I, PD
Active: I, PD		 Management Data Clock: Synchronous clock to the MDIO serial management input/output data. This clock can be asynchronous to the MAC transmit and receive clocks. The maximum clock rate is 24MHz. There is no minimum clock rate.
RX_D1 17 Reset: I, PD, S
Active: O		 RMII Receive Data: Symbols received on the cable are decoded and presented on these pins synchronous to reference clock. These symbols contain valid data when RX_DV is asserted.
RX_D0 18 Reset: I, PD, S
Active: O		 RMII Receive Data: Symbols received on the cable are decoded and presented on these pins synchronous to reference clock. These symbols contain valid data when RX_DV is asserted.
VDDIO 19 Power I/O Supply : 3.3V/1.8V. For decoupling capacitor requirements, refer to the Section 7 section.
CRS_DV 20 Reset: I, PD, S
Active: O		 Carrier Sense / Receive Data Valid: This pin combines the RMII Carrier and Receive Data Valid indications.
GND 21 GND Ground pin
RX_ER 22 Reset: I, PD, S
Active: O		 RMII Receive Error: This pin indicates an error symbol has been detected within a received packet in RMII mode. RX_ER is asserted high synchronously to the rising edge of the reference clock. This pin is not required by the MAC in RMII mode, because the PHY automatically corrupts data on a receive error.
TX_D0 23 Reset: I, PD
Active: I, PD		 RMII Transmit Data: TX_D[1:0] received from the MAC is synchronous to the rising edge of the reference clock.
TX_D1 24 Reset: I, PD
Active: I, PD
(1) The pin functions are defined below:
Type I: Input
Type O: Output
Type I/O: Input/Output
Type PD or PU: Internal Pulldown or Pullup
Type S: Strap Configuration Pin

 
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