SNLU262A december   2019  – june 2023 DP83826I

 

  1.   1
  2.   DP83826EVM User’s Guide
  3.   Trademarks
  4. 1Definitions
  5. 2Introduction
    1. 2.1 Key Features
    2. 2.2 Operation – Quick Setup
      1. 2.2.1 Power Supply
      2. 2.2.2 Power Inputs
      3. 2.2.3 Software
        1. 2.2.3.1 MSP430 Driver
        2. 2.2.3.2 USB-2-MDIO Software
  6. 3Board Setup Details
    1. 3.1 Block Diagram
    2. 3.2 EVM High Level Summary
  7. 4Configurations Options
    1. 4.1 MDIO Register Access
  8. 5EMI Results
    1. 5.1 Setup
    2. 5.2 Results
  9. 6DP83826EVM Schematics
  10. 7DP83826EVM BOM
  11. 8Revision History

2 Introduction

The DP83826 is a low latency, deterministic, and low power Ethernet Physical Layer transceiver with integrated PMD sublayers to support both 10BASE-Te and 100BASE-TX Ethernet protocols. The DP83826 interfaces directly to twisted pair media via an external transformer and offers integrated cable diagnostic tools, built-in self-test and loopback capabilities for ease of use. It interfaces to the MAC layer through a Media Independent Interface (MII) or a Reduced MII (RMII) both in Master and Slave mode. The 50 MHz clock in RMII Master mode is synchronized to the MDI derived clock to improve the system's jitter. The DP83826EVM will demonstrate all features of DP83826. The EVM supports 10BASE-Te and 100BASE-TX Ethernet protocols. The EVM includes connections to use the DP83826 MII and RMII pins through header pins.

Note:

TI is transitioning to use more inclusive terminology. Some language may be different than what you would expect to see for certain technology areas.