SNLU317A
september 2022 – may 2023
DP83867E
1
Abstract
Trademarks
1
Introduction
1.1
Overview
1.2
Hardware Features
1.3
Software Features
1.4
Block Diagram
2
Board Overview
2.1
Components
2.2
PCIe Header Signals
2.2.1
MISC0 Signal Header
2.2.2
MISC1 Signal Header
2.2.3
RGMII Signal Header
3
Quick Start
4
Schematic, Board Layout, and Bill of Materials
4.1
Board Layout
4.2
Schematic
4.3
Bill of Materials
5
Revision History
4.2
Schematic
Figure 4-3
Schematic : PCIe Host Interface
Figure 4-4
Schematic : DP83867 Ethernet PHY #1
Figure 4-5
Schematic : DP83867 Ethernet PHY #2
Figure 4-6
Schematic : Ethernet Fiber interface
Figure 4-7
Schematic : Power, Clock and Configuration