SNLU317A september   2022  – may 2023 DP83867E

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction
    1. 1.1 Overview
    2. 1.2 Hardware Features
    3. 1.3 Software Features
    4. 1.4 Block Diagram
  5. 2Board Overview
    1. 2.1 Components
    2. 2.2 PCIe Header Signals
      1. 2.2.1 MISC0 Signal Header
      2. 2.2.2 MISC1 Signal Header
      3. 2.2.3 RGMII Signal Header
  6. 3Quick Start
  7. 4Schematic, Board Layout, and Bill of Materials
    1. 4.1 Board Layout
    2. 4.2 Schematic
    3. 4.3 Bill of Materials
  8. 5Revision History

1.1 Overview

GUID-20230426-SS0I-QDWG-CRVS-3PZNLZMML75V-low.jpg Figure 1-1 DP83867 Dual-Port TSN PCIe Application Interface Card (Top View)
GUID-20230426-SS0I-DTSV-T51P-QWSDQ8NFX8XV-low.jpg Figure 1-2 DP83867 Dual-Port TSN PCIe Application Interface Card (Bottom View)

The DP83867 Dual-Port TSN PCIe Application Interface Card plugs into the Intel Tiger Lake or Alder Lake reference design through the PCIe interface connector. This is an easy way to evaluate the functionality of the DP83867 Ethernet PHY with the Intel CPU reference design.

Note that the PCIe interface connector is used only as a form factor and uses proprietary interface signal assignment as given by the Intel reference design. The PCIe form factor carries the SGMII signaling for two Ethernet ports, MDIO/MDC, power supply and control signals.

The AIC supports MDIO access via dedicated a SMI interface over the PCIe interface. The two DP83867 PHYs use different MDIO addresses to be addressed via the common interface.

For easy testing and development purpose, the AIC card supports several pin headers for signal probing.

The AIC uses the two RJ45 jack LEDs to show PHY link and speed indication with one LED, and PHY data transfer activity with the second LED.

Note: The AIC card supports resistor and capacitor mounting options to deploy DP83869 Ethernet PHY instead of DP83867 on each Ethernet interface port by using the same PHY footprint on the PCB.