Design Steps

1. Identify the TEC specifications:
   • Specifications for the circuit shown:
     • TEC maximum current (I_max): 2.5A
     • TEC maximum voltage (V_max): 4.5V
2. H-bridge voltage supply selection:
   • Important Considerations:
     • Voltage drops across the FETs (V_FETs)
     • Voltage drop across R_Sense (V_Rsense)
     • Voltage drop across the TEC (V_TEC)
       • The H-bridge voltage supply (V_H-Bridge) should be at least:
         $V_{\mathrm{H-Bridge}}=V_{\mathrm{FETs}}+V_{R_{\mathrm{Sense}}}+V_{\mathrm{TEC}}$
   • In the previous circuit shown, a 5-V supply is used for the H-bridge to give 0.5V of headroom and accommodate for all of the voltage drops.
   • The H-bridge supply may need to be increased if:
     • A higher voltage is needed for the TEC.
     • FETs cannot be turned ON fully and produce significant voltages drops.
3. Bidirectional current-sense amplifier (U1A):
   • The current-sense amplifier senses the current through the TEC using a sense resistor (R_Sense). The output is used as feedback to the control amplifier (U1C) which determines the gate drive strength (TEC current).
   • R_Sense selection:
     • Smaller values of R_Sense give better power dissipation performance and produce a lower voltage drop. Depending on the desired system accuracy, small values require a precision amplifier with great DC performance to accurately read the sense resistor voltage.
     • R_Sense for this circuit was chosen to be 50mΩ. A 50-mΩ resister produces a voltage drop of 125mV at 2.5A. The LMP7704-SP has a typical offset voltage of ±37µV which produces an error of about 0.75mA at peak current.
   • U1A Gain Selection:
     • The current-sense amplifier gain is determined by the resistors R1, R2, R3, and R4
     • In the previous circuit shown, it is desirable to measure the current as a voltage level by adjusting U1A gain. The chosen gain for the current-sense amplifier is G = 20.
       • A TEC current of 2.5A equates to a 125mV across R_Sense. 125mV across R_Sense translates to 2.5V (125mV × 20) at the output of U1A. The gain selection produces a 1-to-1 relationship between the current through the TEC and the output voltage of the current-sense amplifier.
     • Gain selection equations:
       $G_{U1A}=\frac{1}{R_{\mathrm{Sense}}}=\frac{1}{\mathrm{50m\Omega }}=20=\frac{\mathrm{R2}}{\mathrm{R1}}=\frac{\mathrm{20k\Omega }}{\mathrm{1k\Omega }}$
       $\mathrm{R2}=\mathrm{R4\; and\; R1}=\mathrm{R3}$
     • Following the previous equations always results in a 1-to-1 relationship between the TEC current and the output voltage of the current-sense amplifier.
   • Voltage Reference Selection (U1B):
     • A single-supply op amp is not able to measure current bidirectionally unless it has a DC offset. If no offset is used, the output of the amplifier saturates when the current has the opposite sign of the voltage supply of the op amp. This is why a voltage reference is used to generate a DC offset and prevent saturation.
     • Reference voltage value selection:
       • The voltage reference needs to be at least equivalent to the expected maximum current through the TEC. If 2.5A is the rated I_max of the TEC, then at least a 2.5-V reference must be used to account for the current range of –2.5A to 2.5A. It is also paramount to account for the output swing limitation (V_O) of the amplifier.
         $V_{\mathrm{REF}}=R_{\mathrm{Sense}}\times I_{\mathrm{Max}}\times G_{\mathrm{U1A}}+V_O$
       • A reference voltage of 2.75V was chosen due to the amplifier negative output rail limitation of (V–) + 0.2V.
         $V_{\mathrm{REF}}=\mathrm{2.75V}\ge \mathrm{50m\Omega }\times \mathrm{2.5A}\times 20+\mathrm{0.2V}$
         1. The voltage divider formed by R5 and R6 is fed to one of the LMP7704-SP channels (U1B) as a buffer. The voltage divider generates the reference voltage of 2.75V.
            • To adjust the output of the reference, use the following equation:
              $V_{\mathrm{REF}}=\left(\frac{\mathrm{R6}}{\mathrm{R5}+\mathrm{R6}}\right)\times \mathrm{5V}$
            • The accuracy of the voltage reference depends on the tolerance of the resistors in the divider.
         2. With a voltage reference, calculate the output voltage of the current-sense amplifier as follows:
            $V_{\mathrm{out}\left(U1A\right)}=R_{\mathrm{Sense}}\times I_{\mathrm{TEC}}\times G_{U1A}+V_{\mathrm{REF}}$
            • As the current through the TEC goes from –2.5A to 2.5A, the output voltage of the current-sense amplifier goes from 0.25V to 5.25V (2.75V is equivalent to 0A).
         3. If the negative rail output swing limitation of the chosen amplifier is not accounted for, the current-sense amplifier could saturate and cause the rest of the system to saturate to the maximum possible negative current. The value of the saturated current through the TEC could be more than 2.5A and it would depend on the H-bridge supply voltage and gate drive capability.
            • Fortunately, the LMP7704-SP is a rail-to-rail output amplifier so 0.25V is satisfactory to mitigate the output swing limitation. A different amplifier with less swing requires more headroom from the voltage reference.

   • Voltage Supply Selection:

     • The voltage supply of the current-sense amplifier must be above the maximum expected output V_max and the maximum output swing limitation V_O.
     $V_{\mathrm{Supply}}\ge V_{\mathrm{Max}}+V_O$
     $\mathrm{10V}\ge \mathrm{5.25V}+\mathrm{0.2V}$
     • The chosen amplifier supply is 10V which meets these requirements.
     • Failing to consider the positive output swing limitation can result in the system saturating to the maximum positive TEC current. The maximum positive TEC current could be more than 2.5A (similar to the case of saturating to the negative supply mentioned in the Voltage Reference Selection section).
4. Control Amplifier (U1C):
   • The control amplifier U1C controls the gate drive strength (discussed in Gate Drivers (U1C and U1D)). To determine the gate drive strength and direction, it compares the output from the current-sense amplifier to a control input. The control input (V_IN) can come from a PID or an averaged PWM (usually as an output of a temperature control loop). Since an op amp drives its output until both its input terminals are at the same voltage level, V_IN is what determines the desired current level through the TEC.
   • To control the current through the TEC, set the control input, V_IN, to a voltage from 0.25V to 5.25V. The control amplifier output goes as high or as low as needed to reach the point where the feedback (U1A output) and V_IN are at the same level. Calculate the set TEC current level according to the control input voltage (V_IN) and the voltage reference of the current-sense amplifier (V_REF):
     $I_{\mathrm{TEC}}=V_{\mathrm{IN}}-V_{\mathrm{REF}}$
     $I_{\mathrm{TEC}}=V_{\mathrm{IN}}-2.75V$
   • A V_IN of 0.25V means the control amplifier changes its output until –2.5A is sensed through the TEC. Similarly, a 5.25-V input signal means the control amplifier changes its output until 2.5A is sensed through the TEC.
     • This behavior can be susceptible to oscillations; therefore, components R1 and C1 are added to not allow for the output of the control amplifier to change instantaneously. The values were chosen to induce at least 60° of phase margin as shown in the AC Simulation Results section.
5. Gate Drivers (U1C and U1D):
   • The gate drivers are responsible for providing gate signals to each half-bridge.
   • Gate driver functionality:
     • Taking a look at either gate driver and its corresponding half-bridge:
       • When the output of the gate driver is a high voltage this only turns ON the N-channel FET (Q2 or Q4). When the output is a low voltage, the P-channel FET is ON (Q1 or Q3).
         • It is important to consider if there is any point where three FETs can be ON simultaneously. This is discussed in the MOSFET Selection section.
       • An isolation resistor (R_iso) is added to prevent instability when driving the FETs capacitive load. The value of R8 and R16 is calculated with the following equation:
         $R_{\mathrm{iso}}\ge \frac{1}{2\times \pi \times f_{\mathrm{20DB}}\times C_{\mathrm{load}}}$
         $R_{\mathrm{iso}}=\mathrm{100\Omega }\ge \mathrm{80\Omega }\approx \frac{1}{2\times \pi \times \mathrm{248kHz}\times \mathrm{8000pF}}$
         • For more details, see TI Precision Labs - Op Amps: Stability - Capacitive loads.
   • Setting the gate drive maximum output:
     • To set the maximum output voltage of the gate drivers (V_maxDriver), change the reference voltage TL1431-SP (U2) applied to U1D. Ensure that V_maxDriver is within the output swing capability of the chosen amplifier. In this case the LMP7704-SP output swing is 0.2V from the positive rail; therefore, the maximum V_maxDriver is 9.8V.
       • Setting the TL1431-SP (U2) reference:
         $V_{\mathrm{REF(U}2)}=\left(1+\frac{\mathrm{R14}}{\mathrm{R15}}\right)\times \mathrm{2.5V}$
         $V_{\mathrm{REF(U}2)}=\mathrm{4.5V}=(1+\frac{\mathrm{4.95k\Omega }}{\mathrm{6.19k\Omega }})\times \mathrm{2.5V}$
         • R13 is used to limit supply current when biasing the cathode. Ensure that R13 provides more than 1mA to U2:
           $I_{U2}=\frac{V_{\mathrm{Supply}}-V_{\mathrm{REF(U}2)}}{\mathrm{R13}}\ge \mathrm{1mA}$
           $I_{U2}=\mathrm{1.1mA}=\frac{\mathrm{10V}-\mathrm{4.5V}}{\mathrm{5k\Omega }}\ge \mathrm{1mA}$
       • Setting V_maxDriver Voltage:
         $V_{\mathrm{maxDriver}}=\left(1+\frac{\mathrm{R12}}{\mathrm{R11}}\right)\times V_{\mathrm{REF(U}2)}$
         $V_{\mathrm{maxDriver}}=\mathrm{9V}=(1+\frac{\mathrm{10k\Omega }}{\mathrm{10k\Omega }})\times \mathrm{4.5V}$
       • In the previous design shown, the maximum driver output voltage is equivalent to double the reference voltage due to the non-inverting gain being G = 2.
       • Note that V_maxDriver is the maximum voltage the gate driver U1D could ever produce. However, V_maxDriver is not the maximum voltage applied to the H-bridges by the gate drivers to generate 2.5A through the TEC (V_maxGate). V_maxGate depends on the MOSFETs selected and V_H-Bridge. Determine V_maxGate through simulation or by looking at the MOSFET data sheets and identifying the V_GS required to attain I_max. Simulation showed that a maximum V_maxGate of 8V (worst-case FET threshold voltages) is needed to achieve 2.5A through the TEC.
         • Ensure that V_maxDriver is above the maximum V_maxGate by the amount of output swing limitation of the control amplifier (V_O(U1C)):
           $V_{\mathrm{maxDriver}}\ge V_{\mathrm{maxGate}}+V_{O\left(U1C\right)}$
           $V_{\mathrm{maxDriver}}=\mathrm{9V}\ge \mathrm{8V}+\mathrm{0.2V}$
         • V_maxDriver needs to be above V_maxGate to ensure that the control amplifier (U1C) does not saturate into the negative rail.

   • Inverting gate driver signals:

     • It is important to note that if both gate drivers (U1C and U1D) tracked each other, then all 4 FETs will turn ON at the same time. This is undesirable as it causes shoot-through current. The ideal behavior is that only one of the two diagonal pairs of FETs is turned ON. The diagonal pairs being (Q1 and Q4) OR (Q3 and Q2).
       • To achieve this behavior, the output of U1C is connected to the inverting input of U1D. Looking at how this works: U1D defaults its output to V_maxDriver. However, as the minimum 0.25V V_IN is applied, the output of U1C will slightly increase and settle until –2.5A is sensed. This causes the output of U1D to be at V_maxGate. As V_IN changes, the relationship between both gate driver outputs is defined as follows:
       $U1D_{\mathrm{OUT}}=V_{\mathrm{maxDriver}}-U1C_{\mathrm{OUT}}$
       • This causes the outputs to linearly track each other and in opposite directions, that is, when U1D is at 9V then U1C is at 0V.
         1. This is why V_maxDriver needs to be above V_maxGate by V_O(U1C): to avoid a situation where the output of the U1C is at 0V since it can only swing down to 0.2V of the negative rail (GND).
         2. Assuming that the MOSFET threshold voltages are accounted for, this gate driver design ensures that only one of the two aforementioned diagonal pairs is ON during operation.

   • Amplifier selection:

     • Ensure that the op amp chosen has enough output swing to support the desired maximum voltage. The LMP7704-SP can swing to 0.2V of the positive supply (9.8V).
6. MOSFET Selection:
   • The FET threshold voltage is critical to obtaining a working design. During operation, only one pair of the diagonal FETs must be turned ON at a time. The pairs being: (Q1 and Q4) or (Q3 and Q2). If three FETs were to be ON simultaneously, for example – Q1, Q2, and Q4 then the H-bridge supply rail could connect to GND with a very small resistance through Q2 and cause a spike in current known as shoot-through current. This could damage the FET and lead to system failure. To avoid this, it is absolutely crucial to have only one of the diagonal FET pairs turned ON at a time.
     • For the circuit shown, the FETs selected all have a minimum threshold voltage (V_th) of 2V (N-channel) or –2V (P-channel).
       • This means a 2.5-V gate signal, without the resistor divider on the N-channel FETs, can turn ON both the high-side and low-side FET of the same half-bridge and cause shoot-through current.
         • To ensure this does not happen, a voltage divider is added for the N-channel FETs. Choose the voltage divider such that when the P-channel FET is about to turn ON, the N-channel FET, driven by the same gate signal, should be off. For the chosen FETs that have a V_th of 2V, it was chosen that the N-channel FET gate (V_N-Gate­) should be at 1.9V when 3V is an output of a gate driver. Calculate the voltage divider as follows (assume R_TOP = 100kΩ and ensure that V_N-Gate is lower than the minimum N-channel V_th):
           $R_{\mathrm{BOTTOM}}=\frac{\frac{V_{\mathrm{N-Gate}}}{(V_{\mathrm{H-Bridge}}+V_{\mathrm{th}(min)PFET})}}{1–\frac{V_{\mathrm{N-Gate}}}{(V_{\mathrm{H-Bridge}}+V_{\mathrm{th}(min)PFET})}}\times R_{\mathrm{TOP}}; V_{\mathrm{N-Gate}}<V_{\mathrm{th(min)NFET}}$
           $R_{\mathrm{BOTTOM}}=\mathrm{172k\Omega }\approx \frac{\frac{\mathrm{1.9V}}{(\mathrm{5V}+(–\mathrm{2V}\left)\right)}}{1–\frac{\mathrm{1.9V}}{(\mathrm{5V}+(–\mathrm{2V}\left)\right)}}\times 100\mathrm{k\Omega }$
     • With the previously-calculated resistor divider, if a 2.5-V gate signal is applied to turn ON the P-channel FET then the N-channel gate only sees 1.6V and therefore it is off. This ensures only one of the diagonal pairs of FETs is ON during operation.
       • Ensure that the gate can be driven high enough such that the maximum V_th of the FETs (from the data sheet) can still be used with the resistor divider. According to the data sheet, the maximum V_th is 4V. When an absolute maximum V_maxGate (8.8V) signal is applied, the maximum V_N-Gate with the divider is 5.56V. Ensuring turn ON at V_th variation.
         • The absolute maximum V_maxGate without saturating U1C is 8.8V and is derived based on the following equation:
         $V_{\mathrm{maxGate}}\le V_{\mathrm{maxDriver}}–V_{O\left(U1C\right)}$
         $V_{\mathrm{maxGate}}=\mathrm{8.8V}\le \mathrm{9V}–\mathrm{0.2V}$