SNVAA71 October 2023 TPSM63610
As shown in Figure 2-1, use a ceramic bypass capacitor, CBYPS, with a minimum capacitance of 10 μF. The voltage rating must be taken into consideration because this capacitor will experience stress equal to the full voltage range between VIN and VOUT.
For the system to be stable, there must be an input power supply capacitor to help dampen the high-frequency noise that can couple onto the circuit. An electrolytic capacitor with moderate ESR helps dampen any input supply ringing caused by long power leads. When using the TPSM63610EVM, CBULK capacitor must be added across VIN and SYS_GND.
Consider that the inclusion of the CBYPS capacitor introduces an AC path from VIN to VOUT and might worsen the transient response. When VIN is applied to the circuit, this dV/dt across the bypass capacitor creates a current that must return to ground to complete the loop. This current might flow through the internal low-side body diode of the MOSFET and the inductor to return to ground. For this case, it is recommended to have a Schottky diode between -VOUT and SYS GND. If large line transients are expected, increase the output capacitance to keep the output voltage within acceptable levels.