7.3.3.1 Fault Operation

Upon entering a fault condition, the LM3642 will set the appropriate flag in the Flags Register.

7.3.3.2 Flash Time-Out

The Flash Time-Out period sets the amount of time that the Flash Current is being sourced from the current source (LED). The LM3642 has 8 time-out levels ranging 100 ms to 800 ms in 100-ms steps. The Flash Time-Out period is controlled in the Flash Features Register (0x08). Flash Time-Out only applies to the Flash Mode operation. The mode bits in the Enable Register (0x0A) are cleared upon a Flash Time-out.

If an I²C command is used to terminate the flash event, TI recommends selecting a flash time-out level 100 ms above the desired flash duration.

7.3.3.3 Overvoltage Protection (OVP)

The output voltage is limited to typically 5 V (see V_OVP in Electrical Characteristics). In situations such as an open LED, the LM3642 will raise the output voltage in order to keep the LED current at its target value. When V_OUT reaches 5 V (typ.) the overvoltage comparator will trip and turn off the internal NFET. When V_OUT falls below the V_OVP Off Threshold, the LM3642 begins switching again. The mode bits in the Enable Register are not cleared upon an OVP.

7.3.3.4 Current Limit

The LM3642 features selectable inductor current limits that are programmable through the Flash Feature Register of the I²C-compatible interface. When the inductor current limit is reached, the LM3642 will terminate the charging phase of the switching cycle.

Since the current limit is sensed in the NMOS switch, there is no mechanism to limit the current when the device operates in Pass Mode. In Boost Mode or Pass Mode if V_OUT falls below 2.3 V, the part stops switching, and the PFET operates as a current source limiting the current to 300 mA. This prevents damage to the LM3642 and excessive current draw from the battery during output short-circuit conditions. The mode bits in the Enable Register (0x0A) are not cleared upon a Current Limit event.

7.3.3.5 Undervoltage Lockout (UVLO)

The LM3642 has an internal comparator that monitors the voltage at IN which will force the LM3642 into shutdown if the input voltage drops to 2.8 V. If the UVLO monitor threshold is tripped, the UVLO flag bit will be set in the Flags Register. If the input voltage rises above 2.8 V, the LM3642 will not be available for operation until there is an I²C read command initiated for the Flags Register. Upon a read, the flag register will be cleared, and normal operation can resume. This feature can be disabled by writing a ‘0’ to the UVLO EN bit in the Input Voltage Flash Monitor Register. The mode bits in the Enable Register are cleared upon a UVLO event.

7.3.3.6 Thermal Shutdown (TSD)

When the LM3642 device’s die temperature reaches 150°C the boost converter shuts down, and the NFET and PFET turn off, as does the current source (LED). When the thermal shutdown threshold is tripped, a '1' gets written to the corresponding bit of the Flags Register (Thermal Shutdown bit), and the LM3642 will go into standby. The LM3642 will only be allowed to restart after the Flags Register is read, clearing the fault flag. Upon restart, if the die temperature is still above 150°C, the LM3642 will reset the fault flag and re-enter standby. The mode bits in the Enable Register are cleared upon a TSD.

7.3.3.7 LED and/or V_OUT Fault

The LED Fault flag in the Flags Register reads back a '1' if the part is active in Flash or Torch Mode and the LED output or the V_OUT node experiences short condition. The LM3642 determines an LED open condition if the OVP threshold is crossed at the OUT pin while the device is in Flash or Torch Mode. An LED short condition is determined if the voltage at LED goes below 500 mV (typ.) while the device is in Torch or Flash Mode. There is a delay of 256-μs deglitch time before the LED flag is valid and 2.048 ms before the V_OUT flag is valid. This delay is the time between when the Flash or Torch current is triggered and when the LED voltage and the output voltage is sampled. The LED flag can be reset by reading back the flags register. The mode bits in the Enable Register are cleared upon an LED and/or V_OUT fault.

Table 1. Status of Mode Bits

7.5.1.1 Data Validity

The data on SDA line must be stable during the HIGH period of the clock signal (SCL). In other words, state of the data line can only be changed when SCL is LOW.

Figure 12. Data Validity Diagram

A pullup resistor between the controller's VIO line and SDA must be greater than [(VIO – V_OL) / 3 mA] to meet the V_OL requirement on SDA. Using a larger pullup resistor results in lower switching current with slower edges, while using a smaller pullup results in higher switching currents with faster edges.

7.5.1.2 Start and Stop Conditions

START and STOP conditions classify the beginning and the end of the I²C session. A START condition is defined as SDA signal transitioning from HIGH to LOW while SCL line is HIGH. A STOP condition is defined as the SDA transitioning from LOW to HIGH while SCL is HIGH. The I²C master always generates START and STOP conditions. The I²C bus is considered to be busy after a START condition and free after a STOP condition. During data transmission, the I²C master can generate repeated START conditions. First START and repeated START conditions are equivalent, function-wise.

Figure 13. Start and Stop Conditions

7.5.1.3 Transferring Data

Every byte put on the SDA line must be eight bits long, with the most significant bit (MSB) transferred first. Each byte of data has to be followed by an acknowledge bit. The acknowledge related clock pulse is generated by the master. The master releases the SDA line (HIGH) during the acknowledge clock pulse. The LM3642 pulls down the SDA line during the 9th clock pulse, signifying an acknowledge. The LM3642 generates an acknowledge after each byte is received. There is no acknowledge created after data is read from the LM3642.

After the START condition, the I²C master sends a chip address. This address is seven bits long followed by an eighth bit which is a data direction bit (R/W). The LM3642 7-bit address is 0x63. For the eighth bit, a '0' indicates a WRITE and a '1' indicates a READ. The second byte selects the register to which the data will be written. The third byte contains data to write to the selected register.

w = write (SDA = "0")
r = read (SDA = "1")
ack = acknowledge (SDA pulled down by either master or slave)
id = chip address, 63h for LM3642

Figure 14. Write Cycle

7.5.1.4 I²C-Compatible Chip Address

The device address for the LM3642 is 1100011 (63). After the START condition, the I²C-compatible master sends the 7-bit address followed by an eighth read or write bit (R/W). R/W = 0 indicates a WRITE, and R/W = 1 indicates a READ. The second byte following the device address selects the register address to which the data will be written. The third byte contains the data for the selected register.

Figure 15. I²C-Compatible Device Address

7.5.1.5 Transferring Data

Every byte on the SDA line must be eight bits long, with the most significant bit (MSB) transferred first. Each byte of data must be followed by an acknowledge bit (ACK). The acknowledge related clock pulse (9th clock pulse) is generated by the master. The master releases SDA (HIGH) during the 9th clock pulse. The LM3642 pulls down SDA during the 9th clock pulse, signifying an acknowledge. An acknowledge is generated after each byte has been received.

7.6.1.1 Enable Register (0x0A)

7.6.1.2 Flags Register (0x0B)

7.6.1.3 Flash Features Register (0x08)

7.6.1.4 Current Control Register (0x09)

7.6.1.5 Input Voltage Flash Monitor (IVFM) Mode Register (0x01)

Figure 16. Stop and Hold Mode

7.6.1.6 Torch Ramp Time Register (0x06)

7.6.1.7 Silicon Revision Register