SNVU793 September   2021 LM5158

 

  1.   Trademarks
  2. 1Introduction
  3. 2Electrical Parameters
  4. 3Application Schematic
  5. 4EVM Picture
  6. 5Test Setup and Procedure
    1. 5.1 EVM Test Setup Schematic
    2. 5.2 Test Equipment
  7. 6Test Data and Performance Curves
    1. 6.1 Efficiency
    2. 6.2 Output Regulation
    3. 6.3 Steady-State Waveforms
    4. 6.4 Start-Up Waveforms
    5. 6.5 Dynamic Responses
    6. 6.6 Short-Circuit Protection
    7. 6.7 Bode Plots
    8. 6.8 Thermal Image
  8. 7Schematic
  9. 8Bill of Materials
  10. 9EVM Layout

6.2 Output Regulation

GUID-20210816-SS0I-HGHJ-XVBJ-L734D4HXKBZT-low.gifFigure 6-2 Main Output Voltage Regulation Versus Main Output Load (Io2, Io3, Io4 = 10%)
GUID-20210816-SS0I-FXKC-JTFN-6WBGD1XPCF3B-low.gifFigure 6-4 Main Output Voltage Regulation Versus Input Voltage (Io2, Io3, Io4 = 100%)
GUID-20210816-SS0I-F2JX-WQWK-JVJZ1JK0N7RF-low.gifFigure 6-3 Main Output Voltage Regulation Versus Main Output Load (Io2, Io3, Io4 = 100%)
GUID-20210816-SS0I-B0VL-7CJQ-HBFBPMDFSGXM-low.gifFigure 6-5 Voltage Regulation of Isolated Outputs Versus Input Voltage at 10% load