LP873248-Q1 Technical Reference Manual

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1 Technical Reference Manual

This document provides the register bit values for the one-time programmable (OTP) bits of the orderable part number, LP873248RHDRQ1.

1 Introduction

This technical reference manual can be used as a reference for the LP873248-Q1 default register bits after OTP memory download. This technical reference manual does not provide information about the electrical characteristics, external components, package, or the functionality of the device. For this information and the full register map, refer to the

2 OTP Memory Device Settings

This section lists all of the device settings that are downloaded from OTP memory.

Table 2-1 lists the device settings for I²C and OTP revision ID values.

Table 2-1 Device Identification and I²C Settings

	Description	Bit Name	LP873248-Q1
I²C address			61h
DEVICE_ID	Device specific ID code	DEVICE_ID	1h
OTP_ID	Identification code for OTP version	OTP_ID	48h

Table 2-2 lists the device settings for BUCK0 and BUCK1. The maximum allowed slew-rate for BUCKx depends on the output capacitance. Refer to the for output capacitance boundary conditions.

Table 2-2 BUCK0 and BUCK1 OTP Settings

	Description	Bit Name	LP873248-Q1
	Buck phase configuration (2 single phase Bucks or combined 2 phase, denoted as 1+1 or 2-phase)		1+1
	Switching frequency		2 MHz
	Spread spectrum	EN_SPREAD_SPEC	Enabled
BUCK0	Output voltage	BUCK0_VSET	0.800 V
	Enable, EN-pin or I²C register	BUCK0_EN_PIN_CTRL	EN-pin
	Control for BUCK0	BUCK0_EN	High
	Force PWM mode or auto mode	BUCK0_FPWM	Yes
	Force Multiphase	BUCK0_FPWM_MP	No
	Peak current limit	BUCK0_ILIM	3 A
	Maximum load current limit	NA	2 A
	Slew rate	BUCK0_SLEW_RATE	3.8 mV/us
	Startup delay	BUCK0_STARTUP_DELAY	1 ms
	Shutdown delay	BUCK0_SHUTDOWN_DELAY	1 ms
BUCK1	Output voltage	BUCK1_VSET	1.800 V
	Enable, EN-pin or I²C register	BUCK1_EN_PIN_CTRL	EN-pin
	Control for BUCK1	BUCK1_EN	High
	Force PWM mode or auto mode	BUCK1_FPWM	Yes
	Peak current limit	BUCK1_ILIM	3 A
	Maximum load current limit	NA	2 A
	Slew rate	BUCK1_SLEW_RATE	3.8 mV/us
	Startup delay	BUCK1_STARTUP_DELAY	1 ms
	Shutdown delay	BUCK1_SHUTDOWN_DELAY	1 ms

Table 2-3 lists the device settings for LDO0 and LDO1.

Table 2-3 LDO0 and LDO1 OTP Settings

	Description	Bit Name	LP873248-Q1
LDO0	Output voltage	LDO0_VSET	3.300 V
	Enable, EN-pin or I²C register	LDO0_EN_PIN_CTRL	EN-pin
	Control for LDO0	LDO0_EN	High
	Startup delay	LDO0_STARTUP_DELAY	1 ms
	Shutdown delay	LDO0_SHUTDOWN_DELAY	1 ms
LDO1	Output voltage	LDO1_VSET	3.300 V
	Enable, EN-pin or I²C register	LDO1_EN_PIN_CTRL	EN-pin
	Control for LDO1	LDO1_EN	High
	Startup delay	LDO1_STARTUP_DELAY	1 ms
	Shutdown delay	LDO1_SHUTDOWN_DELAY	1 ms

Table 2-4 lists the device settings for GPIOs.

Table 2-4 EN, CLKIN, and GPIO Pin Settings

	Description	Bit Name	LP873248-Q1
EN pin	EN pin pulldown resistor enable or disable	EN_PD	Enabled
CLKIN pin	CLKIN or GPO2 mode selection	CLKIN_PIN_SEL	GPO2
	CLKIN pin pulldown resistor enable or disable (applicable for both CLKIN and GPO2 modes.)	CLKIN_PD	Enabled
	Frequency of external clock when connected to CLKIN	EXT_CLK_FREQ	2 MHz
	Enable for the internal PLL. When PLL disabled, internal RC OSC is used	EN_PLL	Not Used
GPO	GPO output type (push-pull or open drain)	GPO_OD	OD
	Enable, EN-pin or I²C register	GPO_EN_PIN_CTRL	EN-pin
	Control for GPO	GPO_EN	High
	Startup delay	GPO_ STARTUP_ DELAY	2 ms
	Shutdown delay	GPO_ SHUTDOWN_ DELAY	0 ms
GPO2	GPO2 output type (push-pull or open drain)	GPO2_OD	OD
	Enable, EN-pin or I²C register	GPO2_EN_PIN_CTRL	EN-pin
	Control for GPO2	GPO2_EN	High
	Startup delay	GPO2_ STARTUP_ DELAY	0 ms
	Shutdown delay	GPO2_ SHUTDOWN_ DELAY	0 ms

Table 2-5 lists the device protection settings.

Table 2-5 Protections OTP Settings

	Description	Bit Name	LP873248-Q1
Protections	Thermal warning level (125°C or 137°C)	TDIE_WARN_LEVEL	137°C
Protections	Input overvoltage protection	NA	Enabled

Table 2-6 lists the device settings for interrupts. When an interrupt from an event is unmasked, an interrupt is generated on the nINT pin.

Table 2-6 Interrupt Mask Settings

	Interrupt event	Bit Name	LP873248-Q1
General	PGOOD pin changing active to inactive	PGOOD_INT_MASK	Masked
	Sync clock appears or disappears	SYNC_CLK_MASK	Masked
	Thermal warning	TDIE_WARN_MASK	Unmasked
	Load measurement ready	I_MEAS_MASK	Masked
	Register reset	RESET_REG_MASK	Masked
BUCK0	Buck0 PGood active	BUCK0_PGR_MASK	Masked
	Buck0 PGood inactive	BUCK0_PGF_MASK	Masked
	Buck0 current limit	BUCK0_ILIM_MASK	Masked
BUCK1	Buck1 PGood active	BUCK1_PGR_MASK	Masked
	Buck1 PGood inactive	BUCK1_PGF_MASK	Masked
	Buck1 current limit	BUCK1_ILIM_MASK	Masked