SNVU852B September   2023  – June 2024

 

  1.   1
  2.   Description
  3.   Get Started
  4.   Features
  5.   Applications
  6.   6
  7. 1Evaluation Module Overview
    1. 1.1 Introduction
    2. 1.2 Kit Contents
    3. 1.3 Specification
    4. 1.4 Device Information
  8. 2Hardware
    1. 2.1 Connector, Test Point, and Selection Switch Descriptions
      1. 2.1.1 Connector Descriptions
      2. 2.1.2 Jumper Descriptions
      3. 2.1.3 Test Point Descriptions
      4. 2.1.4 Selection Switch Descriptions
        1. 2.1.4.1 S1 and S2 CFG Setting
      5. 2.1.5 I2C Operation
  9. 3Implementation Results
    1. 3.1 Test Setup and Procedure
      1. 3.1.1 Test Setup
      2. 3.1.2 Test Procedure
      3. 3.1.3 Precautions
    2. 3.2 Test Data and Performance Curves
      1. 3.2.1 Thermal Performance
      2. 3.2.2 Efficiency
      3. 3.2.3 Steady State Waveforms
      4. 3.2.4 Step Load Response
      5. 3.2.5 AC Loop Response Curve
  10. 4Hardware Design Files
    1. 4.1 Schematic
    2. 4.2 PCB Layout
    3. 4.3 Bill of Materials
  11. 5Additional Information
    1. 5.1 Trademarks
  12. 6Revision History

2.1.2 Jumper Descriptions

Table 2-2 Jumpers
Reference DesignatorPinsDescriptionDefault Connection
JP1Pin 1 to Pin 2

(GND)

Jumper in position GND and power save mode (PSM) is enabled.
Pin 2 to Pin 3

(VCC)

Jumper in position VCC and FPWM mode is enabled.*
JP2Pin 2 to Pin 3

(VCC)

Jumper in position VCC (SYNC pin tied VCC) and frequency synchronization is disabled.*

Open

Jumper removed and external clock feed in on the SYNC pin. SYNC is enabled.
JP3Pin 1 to Pin 2

(GND)

Jumper in position GND (DTRK pin tied GND) and digital voltage tracking is disabled.*
OpenJumper removed and voltage feed in on the DTRK pin. DTRK is enabled in case the voltage on the DTRK pin is higher than the rising threshold of the VT(DTRK).
JP4Pin 1 to Pin 2

(VEXT)

Jumper in position VEXT and the input from J7-VEXT is connected to the BIAS pin.
Pin 3 to Pin 4

(VIN)

Jumper in position VIN. VIN (J1) is connected to the BIAS pin.*
Pin 5 to Pin 6

(VOUT)

Jumper in position VOUT. VOUT (J2) is connected to the BIAS pin.
JP5Pin 1 to Pin 2

(GND)

Jumper in position GND (EN/UVLO pin tied GND). The LM51772 is disabled.
OpenJumper removed (the EN pin is tied to a resistor divider network consisting of R14 and R15). The EN/UVLO threshold is set with the resistor divider network.*
Pin 2to Pin 3

(VIN)

Jumper in position VCC (EN/UVLO pin tied VCC). The LM51772 is enabled.
JP6Pin 1 / Pin2Connection point for loop stability measurement (Bode plot).
Pin 3GND
Pin 4 to Pin 5Jumper in position selects internal feedback divider.

Open

External Feedback divider is selected

*

JP7

Pin 1 to Pin 2

(GND)

Set nRST to GND: Disable device.
Pin 2 to Pin 3

(VCC)

Set nRST to VCC: Enable device.

*

JP8

Pin 1 to Pin 2

Enable I2C and set I2C Address 6A

Open

Remove jumper to disable I2C operation and set Slope configuration

*

JP9

Pin 1 to Pin 2 (GND)

Do not set jumper, can be used to measure ILIMCOMP signal

Pin 2 to PIN 3 (VCC)

ILIMCOMP connected to VCC. Disable ILIMCOMP

*

JP10

Pin 1 to Pin 2

Set jumper to enable ILIM filter for no DAC

*

Open

Simple ILIM Filter for DAC operation is set. Complex filter can be set with populating R17 and C40.

JP11

Pin 1 to Pin 2

Set jumper to enable config setting for no I2C configuration

*

Open

Remove jumper of I2C operation

JP12

Pin 1 to Pin 2

Set jumper to enable config setting for no I2C operation

*

Open

Remove jumper for I2C operation