SNVU859 June 2024 LP5813
Table 2-27 lists the memory-mapped registers for the Fault_Clear registers. All register offset addresses not listed in Table 2-27 should be considered as reserved locations and the register contents should not be modified.
Address | Acronym | Register Name | Section |
---|---|---|---|
22h | Fault_Clear | Clear the LOD/LSD/TSD flats | Go |
Fault_Clear is shown in Figure 2-22 and described in Table 2-28.
Return to the Summary Table.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | tsd_clear | lsd_clear | lod_clear | ||||
R/W-0h | W1C-0h | W1C-0h | W1C-0h | ||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-3 | RESERVED | R/W | 0h | Reserved |
2 | tsd_clear | W1C | 0h | TSD Fault Status Clear Write 1 to clear and read back 0 |
1 | lsd_clear | W1C | 0h | LSD Fault Status Clear Write 1 to clear and read back 0 |
0 | lod_clear | W1C | 0h | LOD Fault Status Clear Write 1 to clear and read back 0 |