SNVU912 June   2024 LP87524-Q1

 

  1.   1
  2.   , , Technical Reference Manual
  3.   Trademarks
  4. 1Introduction
  5. 2Register Bits Loaded From OTP Memory
  6. 3Revision History

Introduction

This technical reference manual can be used as a reference for the LP875241S-Q1 default register bits after OTP memory download. This technical reference manual does not provide information about the electrical characteristics, external components, package, or the functionality of the device. For this information and the full register map, refer to the LP8752x-Q1 Four-Phase 10-A Buck Converter With Integrated Switches data sheet

Table 1-1 lists the main OTP settings for power rails. Table 2-1 lists the register bits loaded from OTP memory.

Table 1-1 Main OTP Settings for Power Rails
DescriptionBit NameLP875241S-Q1 Value
Device identificationOTP configurationOTP_ID0x19
BUCK0Output voltageBUCK0_VSET900 mV
Enable, EN pin, or I2C registerEN_BUCK0, EN_PIN_CTRL0, BUCK0_EN_PIN_SELECTEN1
Force PWMBUCK0_FPWMYes
Peak current limitILIM03.5 A
Maximum load currentN/A2.5 A
Slew rateSLEW_RATE01.9 mV/µs
BUCK1Output voltageBUCK1_VSET900 mV
Enable, EN pin, or I2C registerEN_BUCK1, EN_PIN_CTRL1, BUCK1_EN_PIN_SELECTEN1
Force PWMBUCK1_FPWMYes
Peak current limitILIM13.5 A
Maximum load currentN/A2.5 A
Slew RateSLEW_RATE11.9 mV/µs
BUCK2Output voltageBUCK2_VSET900 mV
Enable, EN pin, or I2C registerEN_BUCK2, EN_PIN_CTRL2, BUCK2_EN_PIN_SELECTEN3
Force PWMBUCK2_FPWMYes
Peak current limitILIM24 A
Maximum load currentN/A3 A
Slew rateSLEW_RATE21.9 mV/µs
BUCK3Output voltageBUCK3_VSET1000 mV
Enable, EN pin, or I2C registerEN_BUCK3, EN_PIN_CTRL3, BUCK3_EN_PIN_SELECTEN3
Force PWMBUCK3_FPWMYes
Peak current limitILIM33.5 A
Maximum load currentN/A2.5 A
Slew rateSLEW_RATE31.9 mV/µs
Switching frequencyN/A2 MHz
I2C addressN/A0x60
Note:

The maximum total output capacitance (local + POL) per phase (BUCK0, BUCK1, BUCK2, and BUCK3) depends on the slew rate setting. Check the data sheet for the allowed capacitance value.