SPMA078 March 2021 TM4C1290NCPDT , TM4C1290NCPDT , TM4C1290NCZAD , TM4C1290NCZAD , TM4C1292NCPDT , TM4C1292NCPDT , TM4C1292NCZAD , TM4C1292NCZAD , TM4C1294KCPDT , TM4C1294KCPDT , TM4C1294NCPDT , TM4C1294NCPDT , TM4C1294NCZAD , TM4C1294NCZAD , TM4C1297NCZAD , TM4C1297NCZAD , TM4C1299KCZAD , TM4C1299KCZAD , TM4C1299NCZAD , TM4C1299NCZAD , TM4C129CNCPDT , TM4C129CNCPDT , TM4C129CNCZAD , TM4C129CNCZAD , TM4C129DNCPDT , TM4C129DNCPDT , TM4C129DNCZAD , TM4C129DNCZAD , TM4C129EKCPDT , TM4C129EKCPDT , TM4C129ENCPDT , TM4C129ENCPDT , TM4C129ENCZAD , TM4C129ENCZAD , TM4C129LNCZAD , TM4C129LNCZAD , TM4C129XKCZAD , TM4C129XKCZAD , TM4C129XNCZAD , TM4C129XNCZAD
The most difficult part of a flash based EEPROM emulation driver is ensuring data integrity during unexpected loss of power or reset. While the hardware-based state-machine goes a long way to address this concern, it falls short as evidence by erratum MEM#07. Bits may be only partially erased or only partially programmed because the erase or program operation was cut short by power loss or reset. The actual programming time is much shorter than the erase time. (Programming is done with hot carrier injection, erase is done by Fowler-Nordheim tunneling.) Therefore, the most common issue with data integrity is with a partially erased sector. In this case, the sector may appear as totally erased, but some bits are on the threshold between 1 and 0. These bits may flip when being read. To avoid the partially erased sector, two sectors are used. The driver alternates between the sectors when it updates the data. After the data is written, the driver writes the CRC that was calculated from the buffer. The driver then runs a CRC calculation on the data in the EEPROM. Only if the CRC which was calculated on the buffer and then stored and retrieved from the EEPROM matches the CRC that was calculated from the EEPROM contents is the cycle count updated. If there is a mis-match, the write operation fails. The application may choose to rewrite the data. If there is an error indicated by the internal state-machine during a program or erase operation, this software will repeat the operation up to seven times. This is enough times to force a sector copy operation that would resolve corrupt data caused by erratum MEM#07. It is important that the writing of CycleCount3 not trigger a sector copy, as this operation is done after the data was validated. Because of this the seven retries are disabled during that write. A failure writing CycleCount3 will result in the write operation failing.
If the data in a dataset is programmed in the same order every time, the actual write operation which triggers the sector copy will progress down the line from the first word, to the second and eventually the cycle count. To avoid this, we use three copies of the counter. We write the first two instances of the counter before updating an image and update the third instance only after all data and the CRC have been updated. We alternate writing the first or the second instance of the counter first. This way, it will always be a write to one of the first two counters that initiates the sector copy operation.
If there is a power loss or reset during the programming process, that image of data is lost. The previous most recent image of data will be used.
In the read operation the driver calculates the CRC of the data read and compares it to the value stored in the control block. If there is a mismatch, the driver searches for the newest “old” copy of the data that has a good CRC value and reads that data with a return result of FEE_OLD.