Loading [MathJax]/jax/output/SVG/fonts/TeX/fontdata.js
Menu
Product
Email
PDF
Order now
RM46Lx40 16- and 32-Bit RISC Flash Microcontroller
SPNS183C
September 2012 – June 2015
RM46L440
,
RM46L840
PRODUCTION DATA.
CONTENTS
SEARCH
RM46Lx40 16- and 32-Bit RISC Flash Microcontroller
1
Device Overview
1.1
Features
1.2
Applications
1.3
Description
1.4
Functional Block Diagram
2
Revision History
3
Device Comparison
4
Terminal Configuration and Functions
4.1
PGE QFP Package Pinout (144-Pin)
4.2
ZWT BGA Package Ball-Map (337 Ball Grid Array)
4.3
Terminal Functions
4.3.1
PGE Package
4.3.1.1
Multibuffered Analog-to-Digital Converters (MibADC)
4.3.1.2
Enhanced High-End Timer Modules (N2HET)
4.3.1.3
Enhanced Capture Modules (eCAP)
4.3.1.4
Enhanced Quadrature Encoder Pulse Modules (eQEP)
4.3.1.5
Enhanced Pulse-Width Modulator Modules (ePWM)
4.3.1.6
General-Purpose Input / Output (GPIO)
4.3.1.7
Controller Area Network Controllers (DCAN)
4.3.1.8
Local Interconnect Network Interface Module (LIN)
4.3.1.9
Standard Serial Communication Interface (SCI)
4.3.1.10
Inter-Integrated Circuit Interface Module (I2C)
4.3.1.11
Standard Serial Peripheral Interface (SPI)
4.3.1.12
Multibuffered Serial Peripheral Interface Modules (MibSPI)
4.3.1.13
Ethernet Controller
4.3.1.14
System Module Interface
4.3.1.15
Clock Inputs and Outputs
4.3.1.16
Test and Debug Modules Interface
4.3.1.17
Flash Supply and Test Pads
4.3.1.18
Supply for Core Logic: 1.2V nominal
4.3.1.19
Supply for I/O Cells: 3.3V nominal
4.3.1.20
Ground Reference for All Supplies Except VCCAD
4.3.2
ZWT Package
4.3.2.1
Multibuffered Analog-to-Digital Converters (MibADC)
4.3.2.2
Enhanced High-End Timer Modules (N2HET)
4.3.2.3
Enhanced Capture Modules (eCAP)
4.3.2.4
Enhanced Quadrature Encoder Pulse Modules (eQEP)
4.3.2.5
Enhanced Pulse-Width Modulator Modules (ePWM)
4.3.2.6
General-Purpose Input / Output (GPIO)
4.3.2.7
Controller Area Network Controllers (DCAN)
4.3.2.8
Local Interconnect Network Interface Module (LIN)
4.3.2.9
Standard Serial Communication Interface (SCI)
4.3.2.10
Inter-Integrated Circuit Interface Module (I2C)
4.3.2.11
Standard Serial Peripheral Interface (SPI)
4.3.2.12
Multibuffered Serial Peripheral Interface Modules (MibSPI)
4.3.2.13
Ethernet Controller
4.3.2.14
External Memory Interface (EMIF)
4.3.2.15
System Module Interface
4.3.2.16
Clock Inputs and Outputs
4.3.2.17
Test and Debug Modules Interface
4.3.2.18
Flash Supply and Test Pads
4.3.2.19
Reserved
4.3.2.20
No Connects
4.3.2.21
Supply for Core Logic: 1.2V nominal
4.3.2.22
Supply for I/O Cells: 3.3V nominal
4.3.2.23
Ground Reference for All Supplies Except VCCAD
5
Specifications
5.1
Absolute Maximum Ratings Over Operating Free-Air Temperature Range
5.2
ESD Ratings
5.3
Power-On Hours (POH)
5.4
Device Recommended Operating Conditions
5.5
Switching Characteristics Over Recommended Operating Conditions for Clock Domains
5.6
Wait States Required
5.7
Power Consumption Over Recommended Operating Conditions
5.8
Input/Output Electrical Characteristics Over Recommended Operating Conditions
5.9
Thermal Resistance Characteristics
5.10
Output Buffer Drive Strengths
5.11
Input Timings
5.12
Output Timings
5.13
Low-EMI Output Buffers
6
System Information and Electrical Specifications
6.1
Device Power Domains
6.2
Voltage Monitor Characteristics
6.2.1
Important Considerations
6.2.2
Voltage Monitor Operation
6.2.3
Supply Filtering
6.3
Power Sequencing and Power On Reset
6.3.1
Power-Up Sequence
6.3.2
Power-Down Sequence
6.3.3
Power-On Reset: nPORRST
6.3.3.1
nPORRST Electrical and Timing Requirements
6.4
Warm Reset (nRST)
6.4.1
Causes of Warm Reset
6.4.2
nRST Timing Requirements
6.5
ARM Cortex-R4F CPU Information
6.5.1
Summary of ARM Cortex-R4F CPU Features
6.5.2
ARM Cortex-R4F CPU Features Enabled by Software
6.5.3
Dual Core Implementation
6.5.4
Duplicate clock tree after GCLK
6.5.5
ARM Cortex-R4F CPU Compare Module (CCM-R4) for Safety
6.5.6
CPU Self-Test
6.5.6.1
Application Sequence for CPU Self-Test
6.5.6.2
CPU Self-Test Clock Configuration
6.5.6.3
CPU Self-Test Coverage
6.6
Clocks
6.6.1
Clock Sources
6.6.1.1
Main Oscillator
6.6.1.1.1
Timing Requirements for Main Oscillator
6.6.1.2
Low Power Oscillator
6.6.1.2.1
Features
6.6.1.3
Phase Locked Loop (PLL) Clock Modules
6.6.1.3.1
Block Diagram
6.6.1.3.2
PLL Timing Specifications
6.6.1.4
External Clock Inputs
6.6.2
Clock Domains
6.6.2.1
Clock Domain Descriptions
6.6.2.2
Mapping of Clock Domains to Device Modules
6.6.2.3
Special Clock Source Selection Scheme for VCLKA4_DIVR_EMAC
6.6.3
Clock Test Mode
6.7
Clock Monitoring
6.7.1
Clock Monitor Timings
6.7.2
External Clock (ECLK) Output Functionality
6.7.3
Dual Clock Comparators
6.7.3.1
Features
6.7.3.2
Mapping of DCC Clock Source Inputs
6.8
Glitch Filters
6.9
Device Memory Map
6.9.1
Memory Map Diagram
6.9.2
Memory Map Table
6.9.3
Special Consideration for CPU Access Errors Resulting in Imprecise Aborts
6.9.4
Master/Slave Access Privileges
6.9.5
Special Notes on Accesses to Certain Slaves
6.9.6
Parameter Overlay Module (POM) Considerations
6.10
Flash Memory
6.10.1
Flash Memory Configuration
6.10.2
Main Features of Flash Module
6.10.3
ECC Protection for Flash Accesses
6.10.4
Flash Access Speeds
6.10.5
Program Flash
6.10.6
Data Flash
6.11
Tightly Coupled RAM Interface Module
6.11.1
Features
6.11.2
TCRAM ECC Support
6.12
Parity Protection for Accesses to Peripheral RAMs
6.13
On-Chip SRAM Initialization and Testing
6.13.1
On-Chip SRAM Self-Test Using PBIST
6.13.1.1
Features
6.13.1.2
PBIST RAM Groups
6.13.2
On-Chip SRAM Auto Initialization
6.14
External Memory Interface (EMIF)
6.14.1
Features
6.14.2
Electrical and Timing Specifications
6.14.2.1
Asynchronous RAM
6.14.2.2
Synchronous Timing
6.15
Vectored Interrupt Manager
6.15.1
VIM Features
6.15.2
Interrupt Request Assignments
6.16
DMA Controller
6.16.1
DMA Features
6.16.2
Default DMA Request Map
6.17
Real Time Interrupt Module
6.17.1
Features
6.17.2
Block Diagrams
6.17.3
Clock Source Options
6.17.4
Network Time Synchronization Inputs
6.18
Error Signaling Module
6.18.1
Features
6.18.2
ESM Channel Assignments
6.19
Reset / Abort / Error Sources
6.20
Digital Windowed Watchdog
6.21
Debug Subsystem
6.21.1
Block Diagram
6.21.2
Debug Components Memory Map
6.21.3
JTAG Identification Code
6.21.4
Debug ROM
6.21.5
JTAG Scan Interface Timings
6.21.6
Advanced JTAG Security Module
6.21.7
Boundary Scan Chain
7
Peripheral Information and Electrical Specifications
7.1
Enhanced Translator PWM Modules (ePWM)
7.1.1
ePWM Clocking and Reset
7.1.2
Synchronization of ePWMx Time Base Counters
7.1.3
Synchronizing all ePWM Modules to the N2HET1 Module Time Base
7.1.4
Phase-Locking the Time-Base Clocks of Multiple ePWM Modules
7.1.5
ePWM Synchronization with External Devices
7.1.6
ePWM Trip Zones
7.1.6.1
Trip Zones TZ1n, TZ2n, TZ3n
7.1.6.2
Trip Zone TZ4n
7.1.6.3
Trip Zone TZ5n
7.1.6.4
Trip Zone TZ6n
7.1.7
Triggering of ADC Start of Conversion Using ePWMx SOCA and SOCB Outputs
7.1.8
Enhanced Translator-Pulse Width Modulator (ePWMx) Timings
7.2
Enhanced Capture Modules (eCAP)
7.2.1
Clock Enable Control for eCAPx Modules
7.2.2
PWM Output Capability of eCAPx
7.2.3
Input Connection to eCAPx Modules
7.2.4
Enhanced Capture Module (eCAP) Timings
7.3
Enhanced Quadrature Encoder (eQEP)
7.3.1
Clock Enable Control for eQEPx Modules
7.3.2
Using eQEPx Phase Error to Trip ePWMx Outputs
7.3.3
Input Connections to eQEPx Modules
7.3.4
Enhanced Quadrature Encoder Pulse (eQEPx) Timing
7.4
Multibuffered 12bit Analog-to-Digital Converter
7.4.1
Features
7.4.2
Event Trigger Options
7.4.2.1
MIBADC1 Event Trigger Hookup
7.4.2.2
MIBADC2 Event Trigger Hookup
7.4.2.3
Controlling ADC1 and ADC2 Event Trigger Options Using SOC Output from ePWM Modules
7.4.3
ADC Electrical and Timing Specifications
7.4.4
Performance (Accuracy) Specifications
7.4.4.1
MibADC Nonlinearity Errors
7.4.4.2
MibADC Total Error
7.5
General-Purpose Input/Output
7.5.1
Features
7.6
Enhanced High-End Timer (N2HET)
7.6.1
Features
7.6.2
N2HET RAM Organization
7.6.3
Input Timing Specifications
7.6.4
N2HET1-N2HET2 Synchronization
7.6.5
N2HET Checking
7.6.5.1
Internal Monitoring
7.6.5.2
Output Monitoring using Dual Clock Comparator (DCC)
7.6.6
Disabling N2HET Outputs
7.6.7
High-End Timer Transfer Unit (HTU)
7.6.7.1
Features
7.6.7.2
Trigger Connections
7.7
Controller Area Network (DCAN)
7.7.1
Features
7.7.2
Electrical and Timing Specifications
7.8
Local Interconnect Network Interface (LIN)
7.8.1
LIN Features
7.9
Serial Communication Interface (SCI)
7.9.1
Features
7.10
Inter-Integrated Circuit (I2C)
7.10.1
Features
7.10.2
I2C I/O Timing Specifications
7.11
Multibuffered / Standard Serial Peripheral Interface
7.11.1
Features
7.11.2
MibSPI Transmit and Receive RAM Organization
7.11.3
MibSPI Transmit Trigger Events
7.11.3.1
MIBSPI1 Event Trigger Hookup
7.11.3.2
MIBSPI3 Event Trigger Hookup
7.11.3.3
MIBSPI5 Event Trigger Hookup
7.11.4
MibSPI/SPI Master Mode I/O Timing Specifications
7.11.5
SPI Slave Mode I/O Timings
7.12
Ethernet Media Access Controller
7.12.1
Ethernet MII Electrical and Timing Specifications
7.12.2
Ethernet RMII Electrical and Timing Specifications
7.12.3
Management Data Input/Output (MDIO)
8
Device and Documentation Support
8.1
Device and Development-Support Tool Nomenclature
8.2
Documentation Support
8.2.1
Related Documentation from Texas Instruments
8.2.2
Related Links
8.2.3
Community Resources
8.3
Trademarks
8.4
Electrostatic Discharge Caution
8.5
Glossary
8.6
Device Identification
8.6.1
Device Identification Code Register
8.6.2
Die Identification Registers
8.7
Module Certifications
8.7.1
DCAN Certification
8.7.2
LIN Certification
8.7.2.1
LIN Master Mode
8.7.2.2
LIN Slave Mode - Fixed Baud Rate
8.7.2.3
LIN Slave Mode - Adaptive Baud Rate
9
Mechanical Packaging and Orderable Information
9.1
Packaging Information
IMPORTANT NOTICE
search
No matches found.
Full reading width
Full reading width
Comfortable reading width
Expanded reading width
Card for each section
Card with all content
