RM44Lx20 16- and 32-Bit RISC Flash Microcontroller
- SPNS229C October 2014 – November 2016 RM44L520 , RM44L920
  
  PRODUCTION DATA.

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DATA SHEET

RM44Lx20 16- and 32-Bit RISC Flash Microcontroller

1 Device Overview

1.1 Features

High-Performance Microcontroller (MCU) for Safety-Critical Applications
- Dual CPUs Running in Lockstep
- ECC on Flash and RAM Interfaces
- Built-In Self-Test (BIST) for CPU and On-chip RAMs
- Error Signaling Module With Error Pin
- Voltage and Clock Monitoring
ARM® Cortex®-R4F 32-Bit RISC CPU
- 1.66 DMIPS/MHz With 8-Stage Pipeline
- FPU With Single and Double Precision
- 12-Region Memory Protection Unit (MPU)
- Open Architecture With Third-Party Support
Operating Conditions
- Up to 180-MHz System Clock
- Core Supply Voltage (VCC): 1.14 to 1.32 V
- I/O Supply Voltage (VCCIO): 3.0 to 3.6 V
Integrated Memory
- Up to 1MB of Flash With ECC
- 128KB of RAM With ECC
- 64KB of Flash for Emulated EEPROM With ECC
Common Platform Architecture
- Consistent Memory Map Across Family
- Real-Time Interrupt Timer (RTI) OS Timer
- 128-Channel Vectored Interrupt Module (VIM)
- 2-Channel Cyclic Redundancy Checker (CRC)
Direct Memory Access (DMA) Controller
- 16 Channels and 32 Peripheral Requests
- Parity for Control Packet RAM
- DMA Accesses Protected by Dedicated MPU
Frequency-Modulated Phase-Locked Loop (FMPLL) With Built-In Slip Detector
IEEE 1149.1 JTAG, Boundary Scan and ARM CoreSight™ Components
Advanced JTAG Security Module (AJSM)
Up to 64 General-Purpose I/O (GIO) Pins
- Up to 16 GIO Pins With Interrupt Generation Capability
Enhanced Timing Peripherals
- 7 Enhanced Pulse Width Modulator (ePWM) Modules
- 6 Enhanced Capture (eCAP) Modules
- 2 Enhanced Quadrature Encoder Pulse (eQEP) Modules
Two Next Generation High-End Timer (N2HET) Modules
- N2HET1: 32 Programmable Channels
- N2HET2: 18 Programmable Channels
- 160-Word Instruction RAM With Parity Protection Each
- Each N2HET Includes Hardware Angle Generator
- Dedicated High-End Timer Transfer Unit (HTU) for Each N2HET
Two 12-Bit Multibuffered ADC Modules
- ADC1: 24 Channels
- ADC2: 16 Channels
- 16 Shared Channels
- 64 Result Buffers With Parity Protection Each
Multiple Communication Interfaces
- Up to Three CAN Controllers (DCANs)
  - 64 Mailboxes With Parity Protection Each
  - Compliant to CAN Protocol Version 2.0A and 2.0B
- Inter-Integrated Circuit (I²C)
- 3 Multibuffered Serial Peripheral Interfaces (MibSPIs)
  - 128 Words With Parity Protection Each
  - 8 Transfer Groups
- One Standard Serial Peripheral Interface (SPI) Module
- Two UART (SCI) Interfaces, One With Local Interconnect Network (LIN 2.1) Interface Support
Packages
- 144-Pin Quad Flatpack (PGE) [Green]
- 100-Pin Quad Flatpack (PZ) [Green]

1.2 Applications

Industrial Safety Applications
- Industrial Automation
- Safe Programmable Logic Controllers (PLCs)
- Power Generation and Distribution
- Turbines and Windmills
- Elevators and Escalators
Medical Applications
- Ventilators
- Defibrillators
- Infusion and Insulin Pumps
- Radiation Therapy
- Robotic Surgery

1.3 Description

The RM44Lx20 device is part of the Hercules RM series of high-performance industrial-grade ARM® Cortex®-R-based MCUs. Comprehensive documentation, tools, and software are available to assist in the development of IEC 61508 functional safety applications. Start evaluating today with the Hercules RM LaunchPad Development Kit. The RM44Lx20 device has on-chip diagnostic features including: dual CPUs in lockstep; CPU and memory Built-In Self-Test (BIST) logic; ECC on both the flash and the SRAM; parity on peripheral memories; and loopback capability on most peripheral I/Os.

The RM44Lx20 device integrates the ARM Cortex-R4F floating-point CPU which offers an efficient 1.66 DMIPS/MHz, and has configurations which can run up to 180 MHz providing up to 298 DMIPS. The RM44Lx20 device supports the little-endian [LE] format.

The RM44Lx20 device has up to 1MB of integrated flash and 128KB of RAM configurations with single-bit error correction and double-bit error detection. The flash memory on this device is nonvolatile, electrically erasable and programmable, and is implemented with a 64-bit-wide data bus interface. The flash operates on a 3.3-V supply input (same level as the I/O supply) for all read, program, and erase operations. The SRAM supports single-cycle read and write accesses in byte, halfword, word, and doubleword modes throughout the supported frequency range.

The RM44Lx20 device features peripherals for real-time control-based applications, including two Next-Generation High-End Timer (N2HET) timing coprocessors with up to 44 total I/O terminals, seven Enhanced PWM (ePWM) modules with up to 14 outputs, six Enhanced Capture (eCAP) modules, two Enhanced Quadrature Encoder Pulse (eQEP) modules, and two 12-bit Analog-to-Digital Converters (ADCs) supporting up to 24 inputs.

The N2HET is an advanced intelligent timer that provides sophisticated timing functions for real-time applications. The timer is software-controlled, using a reduced instruction set, with a specialized timer micromachine and an attached I/O port. The N2HET can be used for pulse-width-modulated outputs, capture or compare inputs, or general-purpose I/O (GIO). The N2HET is especially well suited for applications requiring multiple sensor information and drive actuators with complex and accurate time pulses. A High-End Timer Transfer Unit (HTU) can transfer N2HET data to or from main memory. A Memory Protection Unit (MPU) is built into the HTU.

The ePWM module can generate complex pulse width waveforms with minimal CPU overhead or intervention. The ePWM is easy to use and supports complementary PWMs and deadband generation. With integrated trip zone protection and synchronization with the on-chip MibADC, the ePWM is ideal for digital motor control applications.

The eCAP module is essential in systems where the accurately timed capture of external events is important. The eCAP can also be used to monitor the ePWM outputs or to generate simple PWM when not needed for capture applications.

The eQEP module is used for direct interface with a linear or rotary incremental encoder to get position, direction, and speed information from a rotating machine as used in high-performance motion and position-control systems.

The device has two 12-bit-resolution MibADCs with 24 total inputs and 64 words of parity-protected buffer RAM each. The MibADC channels can be converted individually or can be grouped by software for sequential conversion sequences. Sixteen inputs are shared between the two MibADCs. There are three separate groups. Each group can be converted once when triggered or configured for continuous conversion mode. The MibADC has a 10-bit mode for use when compatibility with older devices or faster conversion time is desired.

The device has multiple communication interfaces: three MibSPIs; two SPIs; two SCIs, one of which can be used as LIN; up to three DCANs; and one I2C module. The SPI provides a convenient method of serial interaction for high-speed communications between similar shift-register type devices. The LIN supports the Local Interconnect standard 2.0 and can be used as a UART in full-duplex mode using the standard Non-Return-to-Zero (NRZ) format. The DCAN supports the CAN 2.0B protocol standard and uses a serial, multimaster communication protocol that efficiently supports distributed real-time control with robust communication rates of up to 1 Mbps. The DCAN is ideal for applications operating in noisy and harsh environments (for example, automotive and industrial fields) that require reliable serial communication or multiplexed wiring.

The I2C module is a multimaster communication module providing an interface between the microcontroller and an I²C-compatible device through the I²C serial bus. The I2C module supports speeds of 100 and 400 kbps.

A Frequency-Modulated Phase-Locked Loop (FMPLL) clock module is used to multiply the external frequency reference to a higher frequency for internal use. The FMPLL provides one of the six possible clock source inputs to the Global Clock Module (GCM). The GCM manages the mapping between the available clock sources and the device clock domains.

The device also has an external clock prescaler (ECP) circuit that when enabled, outputs a continuous external clock on the ECLK terminal. The ECLK frequency is a user-programmable ratio of the peripheral interface clock (VCLK) frequency. This low-frequency output can be monitored externally as an indicator of the device operating frequency.

The Direct Memory Access (DMA) controller has 16 channels, 32 peripheral requests, and parity protection on its memory. An MPU is built into the DMA to protect memory against erroneous transfers.

The Error Signaling Module (ESM) monitors device errors and determines whether an interrupt or external error signal (nERROR) is asserted when a fault is detected. The nERROR terminal can be monitored externally as an indicator of a fault condition in the microcontroller.

With integrated functional safety features and a wide choice of communication and control peripherals, the RM44Lx20 device is an ideal solution for high-performance, real-time control applications with safety-critical requirements.

Device Information⁽¹⁾

PART NUMBER	PACKAGE	BODY SIZE
RM44L920PGE	LQFP (144)	20.0 mm × 20.0 mm
RM44L920PZ	LQFP (100)	14.0 mm × 14.0 mm
RM44L520PGE	LQFP (144)	20.0 mm × 20.0 mm
RM44L520PZ	LQFP (100)	14.0 mm × 14.0 mm

(1) For more information, see Section 10, Mechanical Packaging and Orderable Information.

1.4 Functional Block Diagram

Figure 1-1 shows the functional block diagram of the device.

NOTE: The block diagram reflects the 144PGE package. Some functions are multiplexed or not available in other packages. For details, see the respective terminal functions table in Section 4.2, Terminal Functions.

Figure 1-1 Functional Block Diagram^(B)

2 Revision History

This data manual revision history highlights the technical changes made to the SPNS229B device-specific data manual to make it an SPNS229C revision.

Scope: Applicable updates to the RM44Lx20 device family, specifically relating to the RM44L920 and RM44L520 devices (Silicon Revision A), which are now in the production data (PD) stage of development have been incorporated.

Changes from October 31, 2015 to November 1, 2016 (from B Revision (October 2015) to C Revision)

GLOBAL: PZ package is now fully qualifiedGo
Section 1.1 (Features): Updated/Changed the GIO pin count in GIO bulletGo
Section 1.1: Updated/Changed the SPI features bulletGo
Section 3.1 (Related Products): Added new section.Go
Section 4.2 (Signal Descriptions): Updated/Changed reference to Technical Reference ManualGo
Table 4-2 (PGE Enhanced High-End Timer Modules (N2HET)): Added a description for pins 14 and 55 (N2HET1_PIN_nDIS and N2HET2_PIN_nDIS, respectively).Go
Table 4-20 (PZ Enhanced High-End Timer Modules (N2HET)): Added Pin 10, GIOA[5] / INT[5] / EXTCLKIN /EPWM1A/N2HET1_PIN_nDISGo
Table 6-20 (Device Memory Map): Updated/Changed the ACTUAL SIZE column value for "Flash Data Space ECC" under Flash Module Bus2 Interface from "160KB" to "128KB".Go
Section 6.19 (Digital Windowed Watchdog): Added Figure 6-13, Digital Windowed Watchdog ExampleGo
Table 7-11 (eCAPx Clock Enable Control): Updated/Changed "ePWM" to "eCAP" in MODULE INSTANCE columnGo
Table 7-15 (eQEPx Clock Enable Control): Updated/Changed "ePWM" to "eQEP" in MODULE INSTANCE columnGo
Table 7-20 (MibADC1 Trigger Event Hookup): Added lead-in paragraph referencing the tableGo
Table 7-21 (MibADC2 Event Trigger Hookup): Added lead-in paragraph referencing the tableGo
Figure 7-11 (ePWM1SOC1A Switch Implementation): Added missing ePWM1 SOC1A detailed switch connection example and lead-in reference sentenceGo
Section 9.1 (Getting Started and Next Steps): Added new sectionGo
Section 9.2 (Device and Development-Support Tool Nomenclature): Moved subsection after "Getting Started and Next Steps" subsection (new)Go
Section 9.10.1 Added the address of the Device ID register.Go

3 Device Comparison

Table 3-1 lists the features of the RM44Lx20 devices.

Table 3-1 RM44Lx20 Device Comparison⁽¹⁾

FEATURES	DEVICES
Generic Part Number	RM46L852ZWT	RM46L852PGE	RM44L920PGE	RM44L920PZ	RM44L520PGE	RM44L520PZ	RM42L432PZ
Package	337 BGA	144 QFP	144 QFP	100 QFP	144 QFP	100 QFP	100 QFP
CPU	ARM Cortex-R4F	ARM Cortex-R4F	ARM Cortex-R4F	ARM Cortex-R4F	ARM Cortex-R4F	ARM Cortex-R4F	ARM Cortex-R4
Frequency (MHz)	220	220	180	120	180	120	100
Flash (KB)	1280	1280	1024	1024	768	768	384
RAM (KB)	192	192	128	128	128	128	32
Data Flash [EEPROM] (KB)	64	64	64	64	64	64	16
USB OHCI + Device	2+0 or 1+1	2+0 or 1+1	–	–	–	–	–
EMAC	10/100	10/100	–	–	–	–	–
FlexRay	–	–	–	–	–	–	–
CAN	3	3	3	2	3	2	2
MibADC 12-bit (Ch)	2 x (24ch)	2 x (24ch)	2 x (24ch)	2 x (16ch)	2 x (24ch)	2 x (16ch)	1 x (16ch)
N2HET (Ch)	2 (44)	2 (40)	2 (40)	2 (21)	2 (40)	2 (21)	1 (19)
ePWM Channels	14	14	14	8	14	8	–
eCAP Channels	6	6	6	4	6	4	–
eQEP Channels	2	2	2	1	2	1	2
MibSPI (CS)	3 (6 + 6 + 4)	3 (5 + 6 + 1)	3 (5 + 6 + 1)	2 (4 + 2)	3 (5 + 6 + 1)	2 (4 + 2)	1 (4)
SPI (CS)	2 (2 + 1)	1 (1)	1 (1)	1 (1)	1 (1)	1 (1)	2 (4 + 4)
SCI (LIN)	2 (1 with LIN)	2 (1 with LIN)	2 (1 with LIN)	1(with LIN)	2 (1 with LIN)	1(with LIN)	1(with LIN)
I2C	1	1	1	–	1	–	–
GPIO (INT)	101 (with 16 interrupt capable)	64 (with 10 interrupt capable)	64 (with 16 interrupt capable)	45 (with 9 interrupt capable)	64 (with 16 interrupt capable)	45 (with 9 interrupt capable)	45 (with 8 interrupt capable)
EMIF	16-bit data	–	–	–	–	–	–
ETM [Trace] (Data)	–	–	–	–	–	–	–
RTP/DMM (Data)	–	–	–	–	–	–	–
Operating Temperature	-40ºC to 105ºC	-40ºC to 105ºC	-40ºC to 105ºC	-40ºC to 105ºC	-40ºC to 105ºC	-40ºC to 105ºC	-40ºC to 105ºC
Core Supply (V)	1.14 V – 1.32 V	1.14 V – 1.32 V	1.14 V – 1.32 V	1.14 V – 1.32 V	1.14 V – 1.32 V	1.14 V – 1.32 V	1.14 V – 1.32 V
I/O Supply (V)	3.0 V – 3.6 V	3.0 V – 3.6 V	3.0 V – 3.6 V	3.0 V – 3.6 V	3.0 V – 3.6 V	3.0 V – 3.6 V	3.0 V – 3.6 V

(1) Bolding denotes a superset device. For additional device variants, see www.ti.com/rm

3.1 Related Products

For information about other devices in this family of products or related products, see the following links.

Products for RM 16-Bit and 32-Bit MCUs

An expansive portfolio of software and pin-compatible high-performance ARM^® Cortex^®-R-based MCU products from 80 MHz up to 300 MHz with on-chip features that prove a high level of diagnostic coverage, as well as provide scalability to address a wide range of applications.

Companion Products for RM44L920/RM44L520

Review products that are frequently purchased or used with this product.

4 Terminal Configuration and Functions

4.1 Pin Diagrams

4.1.1 PGE QFP Package Pinout (144-Pin)

A. Pins can have multiplexed functions. Only the default function is shown in Figure 4-1.

Figure 4-1 PGE QFP Package Pinout (144-Pin)

4.1.2 PZ QFP Package Pinout (100-Pin)

Figure 4-2 PZ QFP Package Pinout (100-Pin)

4.2 Signal Descriptions

The signal descriptions section shows pin information in module function order per package.

Section 4.2.1 and Section 4.2.2 identify the external signal names, the associated pin or ball numbers along with the mechanical package designator, the pin or ball type (Input, Output, I/O, Power, or Ground), whether the pin or ball has any internal pullup/pulldown, whether the pin or ball can be configured as a GIO, and a functional pin or ball description. The first signal name listed is the primary function for that terminal (pin or ball). The signal name in Bold is the function being described. For information on how to select between different multiplexed functions, see Section 4.3, Pin Multiplexing or see the I/O Multiplexing and Control Module (IOMM) chapter of the RM44Lx 16/32-Bit RISC Flash Microcontroller Technical Reference Manual (SPNU608).

NOTE

All I/O signals except nRST are configured as inputs while nPORRST is low and immediately after nPORRST goes high.

All output-only signals are configured as high impedance while nPORRST is low, and are configured as outputs immediately after nPORRST goes high.

While nPORRST is low, the input buffers are disabled, and the output buffers are high impedance.

In the Terminal Functions tables of Section 4.2.1 and Section 4.2.2, the RESET PULL STATE is the state of the pullup or pulldown while nPORRST is low and immediately after nPORRST goes high. The default pull direction may change when software configures the pin for an alternate function. The PULL TYPE is the type of pull asserted when the signal name in bold is enabled for the given terminal.

4.2.1 PGE Package Terminal Functions

4.2.1.1 Multibuffered Analog-to-Digital Converters (MibADCs)

Table 4-1 PGE Multibuffered Analog-to-Digital Converters (MibADC1, MibADC2)

Terminal		Signal Type	Reset Pull State	Pull Type	Description
Signal Name	144 PGE	Signal Type	Reset Pull State	Pull Type	Description
ADREFHI⁽¹⁾	66	Power	–	None	ADC high reference supply
ADREFLO⁽¹⁾	67	Power			ADC low reference supply
VCCAD⁽¹⁾	69	Power			Operating supply for ADC
VSSAD⁽¹⁾	68	Ground
AD1EVT	86	I/O	Pulldown	Programmable, 20 µA	ADC1 event trigger input, or GIO
MIBSPI3NCS[0]/AD2EVT/GIOB[2]/ EQEP1I/N2HET2_PIN_nDIS	55	I/O	Pullup	Programmable, 20 µA	ADC2 event trigger input, or GIO
AD1IN[0]	60	Input	–	None	ADC1 analog input
AD1IN[01]	71
AD1IN[02]	73
AD1IN[03]	74
AD1IN[04]	76
AD1IN[05]	78
AD1IN[06]	80
AD1IN[07]	61
AD1IN[08] / AD2IN[08]	83	Input	–	None	ADC1/ADC2 shared analog inputs
AD1IN[09] / AD2IN[09]	70
AD1IN[10] / AD2IN[10]	72
AD1IN[11] / AD2IN[11]	75
AD1IN[12] / AD2IN[12]	77
AD1IN[13] / AD2IN[13]	79
AD1IN[14] / AD2IN[14]	82
AD1IN[15] / AD2IN[15]	85
AD1IN[16] / AD2IN[0]	58
AD1IN[17] / AD2IN[01]	59
AD1IN[18] / AD2IN[02]	62
AD1IN[19] / AD2IN[03]	63
AD1IN[20] / AD2IN[04]	64
AD1IN[21] / AD2IN[05]	65
AD1IN[22] / AD2IN[06]	81
AD1IN[23] / AD2IN[07]	84
MIBSPI3SOMI[0]/AWM1_EXT_ENA/ECAP2	51	Output	Pullup	–	AWM1 external analog mux enable
MIBSPI3SIMO[0]/AWM1_EXT_SEL[0]/ECAP3	52	Output	Pullup	–	AWM1 external analog mux select line0
MIBSPI3CLK/AWM1_EXT_SEL[1]/EQEP1A	53	Output	Pullup	–	AWM1 external analog mux select line0

(1) The ADREFHI, ADREFLO, VCCAD and VSSAD connections are common for both ADC cores.

4.2.1.2 Enhanced High-End Timer (N2HET) Modules

Table 4-2 PGE Enhanced High-End Timer (N2HET) Modules

TERMINAL		SIGNAL TYPE	RESET PULL STATE	PULL TYPE	DESCRIPTION
SIGNAL NAME	144 PGE	SIGNAL TYPE	RESET PULL STATE	PULL TYPE	DESCRIPTION
N2HET1[0]/SPI4CLK/EPWM2B	25	I/O	Pulldown	Programmable, 20 µA	N2HET1 timer input capture or output compare, or GIO. Each terminal has a suppression filter with a programmable duration.
N2HET1[01]/SPI4NENA/N2HET2[8]/EQEP2A	23
N2HET1[02]/SPI4SIMO[0]/EPWM3A	30
N2HET1[03]/SPI4NCS[0]/N2HET2[10]/EQEP2B	24
N2HET1[04]/EPWM4B	36
N2HET1[05]/SPI4SOMI[0]/N2HET2[12]/EPWM3B	31
N2HET1[06]/SCIRX/EPWM5A	38
N2HET1[07]/N2HET2[14]/EPWM7B	33
N2HET1[08]/MIBSPI1SIMO[1]/	106
N2HET1[09]/N2HET2[16]/EPWM7A	35
N2HET1[10]/nTZ3	118
N2HET1[11]/MIBSPI3NCS[4]/N2HET2[18]/EPWM1SYNCO	6
N2HET1[12]	124
N2HET1[13]/SCITX/EPWM5B	39
N2HET1[14]	125
N2HET1[15]/MIBSPI1NCS[4]/ECAP1	41
N2HET1[16]/EPWM1SYNCI/EPWM1SYNCO	139
MIBSPI1NCS[1]/N2HET1[17]/EQEP1S	130		Pullup
N2HET1[18]/EPWM6A	140		Pulldown
MIBSPI1NCS[2]/N2HET1[19]	40		Pullup
N2HET1[20]/EPWM6B	141		Pulldown
N2HET1[22]	15		Pulldown
MIBSPI1NENA/N2HET1[23]/ECAP4	96		Pullup
N2HET1[24]/MIBSPI1NCS[5]	91		Pulldown
MIBSPI3NCS[1]/N2HET1[25]	37		Pullup
N2HET1[26]	92		Pulldown
MIBSPI3NCS[2]/I2CSDA/N2HET1[27]/nTZ2	4		Pullup
N2HET1[28]	107		Pulldown
MIBSPI3NCS[3]/I2CSCL/N2HET1[29]/nTZ1	3		Pullup
N2HET1[30]/EQEP2S	127		Pulldown
MIBSPI3NENA/MIBSPI3NCS[5]/N2HET1[31]/EQEP1B	54		Pullup
GIOA[5]/EXTCLKIN1/EPWM1A/N2HET1_PIN_nDIS	14		Pulldown		Disable selected PWM outputs
GIOA[2]/N2HET2[0]/EQEP2I	9	I/O	Pulldown	Programmable, 20 µA	N2HET2 timer input capture or output compare, or GIO Each terminal has a suppression filter with a programmable duration.
GIOA[6]/N2HET2[4]/EPWM1B	16
GIOA[7]/N2HET2[6]EPWM2A	22
N2HET1[01]/SPI4NENA//N2HET2[8]	23
N2HET1[03]/SPI4NCS[0]/N2HET2[10]/EQEP2B	24
N2HET1[05]/SPI4SOMI[0]/N2HET2[12]/EQEP3B	31
N2HET1[07]/N2HET2[14]/EPWM7B	33
N2HET1[09]/N2HET2[16]	35
N2HET1[11]/MIBSPI3NCS[4]/N2HET2[18]/EPWM1SYNCO	6
MIBSPI3NCS[0]/AD2EVT/GIOB[2]/EQEP1l/N2HET2_PIN_nDIS	55		Pullup		Disable selected PWM outputs

4.2.1.3 Enhanced Capture Modules (eCAP)

Table 4-3 PGE Enhanced Capture Modules (eCAP)⁽¹⁾

TERMINAL		SIGNAL TYPE	RESET PULL STATE	PULL TYPE	DESCRIPTION
SIGNAL NAME	144 PGE	SIGNAL TYPE	RESET PULL STATE	PULL TYPE	DESCRIPTION
N2HET1[15]/MIBSPI1NCS[4]/ECAP1	41	I/O	Pulldown	Fixed, 20 µA	Enhanced Capture Module 1 I/O
MIBSPI3SOMI[0]/AWM1_EXT_ENA/ECAP2	51		Pullup		Enhanced Capture Module 2 I/O
MIBSPI3SIMO[0]/AWM1_EXT_SEL[0]/ECAP3	52				Enhanced Capture Module 3 I/O
MIBSPI1NENA/N2HET1[23]/ECAP4	96				Enhanced Capture Module 4 I/O
MIBSPI5NENA/MIBSPI5SOMI[1]/ECAP5	97				Enhanced Capture Module 5 I/O
MIBSPI1NCS[0]/MIBSPI1SOMI[1]/ECAP6	105				Enhanced Capture Module 6 I/O

(1) These signals, when used as inputs, are double-synchronized and then optionally filtered with a 6-cycle VCLK4-based counter.

4.2.1.4 Enhanced Quadrature Encoder Pulse Modules (eQEP)

Table 4-4 PGE Enhanced Quadrature Encoder Pulse Modules (eQEP)⁽¹⁾

TERMINAL		SIGNAL TYPE	RESET PULL STATE	PULL TYPE	DESCRIPTION
SIGNAL NAME	144 PGE	SIGNAL TYPE	RESET PULL STATE	PULL TYPE	DESCRIPTION
MIBSPI3CLK/AWM1_EXT_SEL[1]/EQEP1A	53	Input	Pullup	Fixed, 20 µA	Enhanced QEP1 Input A
MIBSPI3NENA/MIBSPI3NCS[5]/N2HET1[31]/EQEP1B	54	Input			Enhanced QEP1 Input B
MIBSPI3NCS[0]/AD2EVT/GIOB[2]/EQEP1I/N2HET2_PIN_nDIS	55	I/O			Enhanced QEP1 Index
MIBSPI1NCS[1]/N2HET1[17]//EQEP1S	130	I/O			Enhanced QEP1 Strobe
N2HET1[01]/SPI4NENA/N2HET2[8]/EQEP2A	23	Input	Pulldown		Enhanced QEP2 Input A
N2HET1[03]/SPI4NCS[0]/N2HET2[10]/EQEP2B	24	Input			Enhanced QEP2 Input B
GIOA[2]/N2HET2[0]/EQEP2I	9	I/O			Enhanced QEP2 Index
N2HET1[30]/EQEP2S	127	I/O			Enhanced QEP2 Strobe

(1) These signals are double-synchronized and then optionally filtered with a 6-cycle VCLK4-based counter.

4.2.1.5 Enhanced Pulse-Width Modulator Modules (ePWM)

Table 4-5 PGE Enhanced Pulse-Width Modulator Modules (ePWM)

TERMINAL		SIGNAL TYPE	RESET PULL STATE	PULL TYPE	DESCRIPTION
SIGNAL NAME	144 PGE	SIGNAL TYPE	RESET PULL STATE	PULL TYPE	DESCRIPTION
GIOA[5]/EXTCLKIN1/EPWM1A/N2HET1_PIN_nDIS	14	Output	Pulldown	–	Enhanced PWM1 Output A
GIOA[6]/N2HET2[4]/EPWM1B	16				Enhanced PWM1 Output B
N2HET1[11]/MIBSPI3NCS[4]/N2HET2[18]/EPWM1SYNCO	6				External ePWM Sync Pulse Output
N2HET1[16]/EPWM1SYNCI/EPWM1SYNCO	139	Input	Pullup	Fixed, 20 µA	External ePWM Sync Pulse Output
GIOA[7]/N2HET2[6]/EPWM2A	22	Output	Pulldown	–	Enhanced PWM2 Output A
N2HET1[0]/SPI4CLK/EPWM2B	25				Enhanced PWM2 Output B
N2HET1[02]/SPI4SIMO[0]/EPWM3A	30				Enhanced PWM3 Output A
N2HET1[05]/SPI4SOMI[0]/N2HET2[12]/EPWM3B	31				Enhanced PWM3 Output B
MIBSPI5NCS[0]/EPWM4A	32	Output	Pullup	–	Enhanced PWM4 Output A
N2HET1[04]/EPWM4B	36	Output	Pulldown	–	Enhanced PWM4 Output B
N2HET1[06]/SCIRX/EPWM5A	38				Enhanced PWM5 Output A
N2HET1[13]/SCITX/EPWM5B	39				Enhanced PWM5 Output B
N2HET1[18]/EPWM6A	140				Enhanced PWM6 Output A
N2HET1[20]/EPWM6B	141				Enhanced PWM6 Output B
N2HET1[09]/N2HET2[16]/EPWM7A	35				Enhanced PWM7 Output A
N2HET1[07]/N2HET2[14]/EPWM7B	33				Enhanced PWM7 Output B
MIBSPI3NCS[3]/I2CSCL/N2HET1[29]/nTZ1	3	Input	Pullup	Fixed, 20 µA	Trip Zone Inputs 1, 2 and 3. These signals are either connected asynchronously to the ePWMx trip zone inputs, or double-synchronized with VCLK4, or double-synchronized and then filtered with a 6-cycle VCLK4-based counter before connecting to the ePWMx trip zone inputs.
MIBSPI3NCS[2]/I2CSDA/N2HET1[27]/nTZ2	4		Pullup
N2HET1[10]/nTZ3	118		Pulldown

4.2.1.6 General-Purpose Input/Output (GIO)

Table 4-6 PGE General-Purpose Input/Output (GIO)

Terminal		Signal Type	Reset Pull State	Pull Type	Description
Signal Name	144 PGE	Signal Type	Reset Pull State	Pull Type	Description
GIOA[0]	2	I/O	Pulldown	Programmable, 20 µA	General-purpose I/O. All GIO terminals are capable of generating interrupts to the CPU on rising / falling / both edges.
GIOA[1]	5
GIOA[2]/N2HET2[0]/EQEPII	9
GIOA[5]/EXTCLKIN1/EPWM1A/N2HET1_PIN_nDIS	14
GIOA[6]/N2HET2[4]/EPWM1B	16
GIOA[7]/N2HET2[6]/EPWM2A	22
GIOB[0]	126
GIOB[1]	133
GIOB[2]	142
MIBSPI3NCS[0]/AD2EVT/GIOB[2]/EQEP1I/N2HET2_PIN_nDIS	55⁽¹⁾		Pullup
GIOB[3]	1		Pulldown

(1) GIOB[2] cannot output a level on to pin 55. Only the input functionality is supported so that the application can generate an interrupt whenever the N2HET2_PIN_nDIS is asserted (driven low). Also, a pullup is enabled on the input. This is not programmable using the GIO module control registers.

4.2.1.7 Controller Area Network Controllers (DCAN)

Table 4-7 PGE Controller Area Network Controllers (DCAN)

Terminal		Signal Type	Reset Pull State	Pull Type	Description
Signal Name	144 PGE	Signal Type	Reset Pull State	Pull Type	Description
CAN1RX	90	I/O	Pullup	Programmable, 20 µA	CAN1 receive, or GIO
CAN1TX	89				CAN1 transmit, or GIO
CAN2RX	129				CAN2 receive, or GIO
CAN2TX	128				CAN2 transmit, or GIO
CAN3RX	12				CAN3 receive, or GIO
CAN3TX	13				CAN3 transmit, or GIO

4.2.1.8 Local Interconnect Network Interface Module (LIN)

Table 4-8 PGE Local Interconnect Network Interface Module (LIN)

Terminal		Signal Type	Reset Pull State	Pull Type	Description
Signal Name	144 PGE	Signal Type	Reset Pull State	Pull Type	Description
LINRX	131	I/O	Pullup	Programmable, 20 µA	LIN receive, or GIO
LINTX	132	I/O	Pullup	Programmable, 20 µA	LIN transmit, or GIO

4.2.1.9 Standard Serial Communication Interface (SCI)

Table 4-9 PGE Standard Serial Communication Interface (SCI)

Terminal		Signal Type	Reset Pull State	Pull Type	Description
Signal Name	144 PGE	Signal Type	Reset Pull State	Pull Type	Description
N2HET1[06]/SCIRX/EPWM5A	38	I/O	Pulldown	Programmable, 20 µA	SCI receive, or GIO
N2HET1[13]/SCITX/EPWM5B	39	I/O	Pulldown	Programmable, 20 µA	SCI transmit, or GIO

4.2.1.10 Inter-Integrated Circuit Interface Module (I2C)

Table 4-10 PGE Inter-Integrated Circuit Interface Module (I2C)

Terminal		Signal Type	Reset Pull State	Pull Type	Description
Signal Name	144 PGE	Signal Type	Reset Pull State	Pull Type	Description
MIBSPI3NCS[2]/I2CSDA/N2HET1[27]/nTZ2	4	I/O	Pullup	Programmable, 20 µA	I2C serial data, or GIO
MIBSPI3NCS[3]/I2CSCL/N2HET1[29]/nTZ1	3	I/O	Pullup	Programmable, 20 µA	I2C serial clock, or GIO

4.2.1.11 Standard Serial Peripheral Interface (SPI)

Table 4-11 PGE Standard Serial Peripheral Interface (SPI)

Terminal		Signal Type	Reset Pull State	Pull Type	Description
Signal Name	144 PGE	Signal Type	Reset Pull State	Pull Type	Description
N2HET1[0]/SPI4CLK/EPWM2B	25	I/O	Pulldown	Programmable, 20 µA	SPI4 clock, or GIO
N2HET1[03]/SPI4NCS[0]/N2HET2[10]/EQEP2B	24				SPI4 chip select, or GIO
N2HET1[01]/SPI4NENA/N2HET2[8]/EQEP2A	23				SPI4 enable, or GIO
N2HET1[02]/SPI4SIMO[0]/EPWM3A	30				SPI4 slave-input master-output, or GIO
N2HET1[05]/SPI4SOMI[0]/N2HET2[12]/EPWM3B	31				SPI4 slave-output master-input, or GIO

4.2.1.12 Multibuffered Serial Peripheral Interface Modules (MibSPI)

Table 4-12 PGE Multibuffered Serial Peripheral Interface Modules (MibSPI)

Terminal		Signal Type	Reset Pull State	Pull Type	Description
Signal Name	144 PGE	Signal Type	Reset Pull State	Pull Type	Description
MIBSPI1CLK	95	I/O	Pullup	Programmable, 20 µA	MibSPI1 clock, or GIO
MIBSPI1NCS[0]/MIBSPI1SOMI[1]/ECAP6	105				MibSPI1 chip select, or GIO
MIBSPI1NCS[1]/N2HET1[17]//EQEP1S	130
MIBSPI1NCS[2]/N2HET1[19]/	40
N2HET1[15]/MIBSPI1NCS[4]/ECAP1	41		Pulldown	Programmable, 20 µA	MibSPI1 chip select, or GIO
N2HET1[24]/MIBSPI1NCS[5]	91		Pulldown	Programmable, 20 µA	MibSPI1 chip select, or GIO
MIBSPI1NENA/N2HET1[23]/ECAP4	96		Pullup	Programmable, 20 µA	MibSPI1 enable, or GIO
MIBSPI1SIMO[0]	93		Pullup	Programmable, 20 µA	MibSPI1 slave-in master-out, or GIO
N2HET1[08]/MIBSPI1SIMO[1]	106		Pulldown	Programmable, 20 µA	MibSPI1 slave-in master-out, or GIO
MIBSPI1SOMI[0]	94		Pullup	Programmable, 20 µA	MibSPI1 slave-out master-in, or GIO
MIBSPI1NCS[0]/MIBSPI1SOMI[1]/ECAP6	105		Pullup	Programmable, 20 µA	MibSPI1 slave-out master-in, or GIO
MIBSPI3CLK/AWM1_EXT_SEL[1]/EQEP1A	53	I/O	Pullup	Programmable, 20 µA	MibSPI3 clock, or GIO
MIBSPI3NCS[0]/AD2EVT/GIOB[2]/EQEP1I/N2HET2_PIN_nDIS	55				MibSPI3 chip select, or GIO
MIBSPI3NCS[1]/N2HET1[25]	37
MIBSPI3NCS[2]/I2CSDA/N2HET1[27]/nTZ2	4
MIBSPI3NCS[3]/I2CSCL/N2HET1[29]/nTZ1	3
N2HET1[11]/MIBSPI3NCS[4]/N2HET2[18]/EPWM1SYNCO	6		Pulldown	Programmable, 20 µA	MibSPI3 chip select, or GIO
MIBSPI3NENA /MIBSPI3NCS[5]/N2HET1[31]/EQEP1B	54		Pullup	Programmable, 20 µA	MibSPI3 chip select, or GIO
MIBSPI3NENA/MIBSPI3NCS[5]/N2HET1[31]/EQEP1B	54				MibSPI3 enable, or GIO
MIBSPI3SIMO[0]/AWM1_EXT_SEL[0]/ECAP3	52				MibSPI3 slave-in master-out, or GIO
MIBSPI3SOMI[0]/AWM1_EXT_ENA/ECAP2	51				MibSPI3 slave-out master-in, or GIO
MIBSPI5CLK	100	I/O	Pullup	Programmable, 20 µA	MibSPI5 clock, or GIO
MIBSPI5NCS[0]/EPWM4A	32				MibSPI5 chip select, or GIO
MIBSPI5NENA/MIBSPI5SOMI[1]/ECAP5	97				MibSPI5 enable, or GIO
MIBSPI5SIMO[0]/MIBSPI5SOMI[2]	99				MibSPI5 slave-in master-out, or GIO
MIBSPI5SOMI[0]	98				MibSPI5 slave-out master-in, or GIO
MIBSPI5NENA/MIBSPI5SOMI[1]/ECAP5	97				MibSPI5 SOMI[0], or GIO
MIBSPI5SIMO[0]/MIBSPI5SOMI[2]	99				MibSPI5 SOMI[0], or GIO

4.2.1.13 System Module Interface

Table 4-13 PGE System Module Interface

TERMINAL		SIGNAL TYPE	RESET PULL STATE	PULL TYPE	DESCRIPTION
SIGNAL NAME	144 PGE	SIGNAL TYPE	RESET PULL STATE	PULL TYPE	DESCRIPTION
nPORRST	46	Input	Pulldown	100 µA	Power-on reset, cold reset External power supply monitor circuitry must drive nPORRST low when any of the supplies to the microcontroller fall out of the specified range. This terminal has a glitch filter. See Section 6.8.
nRST	116	I/O	Pullup	100 µA	System reset, warm reset, bidirectional. The internal circuitry indicates any reset condition by driving nRST low. The external circuitry can assert a system reset by driving nRST low. To ensure that an external reset is not arbitrarily generated, TI recommends that an external pullup resistor is connected to this terminal. This terminal has a glitch filter. See Section 6.8.
nERROR	117	I/O	Pulldown	20 µA	ESM Error Signal Indicates error of high severity. See Section 6.8.

4.2.1.14 Clock Inputs and Outputs

Table 4-14 PGE Clock Inputs and Outputs

Terminal		Signal Type	Reset Pull State	Pull Type	Description
Signal Name	144 PGE	Signal Type	Reset Pull State	Pull Type	Description
OSCIN	18	Input	–	None	From external crystal/resonator, or external clock input
KELVIN_GND	19	Input			Kelvin ground for oscillator
OSCOUT	20	Output			To external crystal/resonator
ECLK	119	I/O	Pulldown	Programmable, 20 µA	External prescaled clock output, or GIO.
GIOA[5]/EXTCLKIN1/EPWM1A /N2HET1_PIN_nDIS	14	Input	Pulldown	20 µA	External clock input #1

4.2.1.15 Test and Debug Modules Interface

Table 4-15 PGE Test and Debug Modules Interface

Terminal		Signal Type	Reset Pull State	Pull Type	Description
Signal Name	144 PGE	Signal Type	Reset Pull State	Pull Type	Description
TEST	34	Input	Pulldown	Fixed, 100 µA	Test enable. This terminal must be connected to ground directly or via a pulldown resistor.
nTRST	109	Input	Pulldown	Fixed, 100 µA	JTAG test hardware reset
RTCK	113	Output	-	None	JTAG return test clock
TCK	112	Input	Pulldown	Fixed, 100 µA	JTAG test clock
TDI	110	Input	Pullup		JTAG test data in
TDO	111	Output	Pulldown		JTAG test data out
TMS	108	Input	Pullup		JTAG test select

4.2.1.16 Flash Supply and Test Pads

Table 4-16 PGE Flash Supply and Test Pads

Terminal		Signal Type	Reset Pull State	Pull Type	Description
Signal Name	144 PGE	Signal Type	Reset Pull State	Pull Type	Description
VCCP	134	3.3-V Power	–	None	Flash pump supply
FLTP1	7	–	–	None	Flash test pads. These terminals are reserved for TI use only. For proper operation these terminals must connect only to a test pad or not be connected at all [no connect (NC)].
FLTP2	8	–	–	None

4.2.1.17 Supply for Core Logic: 1.2V nominal

Table 4-17 PGE Supply for Core Logic: 1.2V nominal

Terminal		Signal Type	Reset Pull State	Pull Type	Description
Signal Name	144 PGE	Signal Type	Reset Pull State	Pull Type	Description
VCC	17	1.2-V Power	–	None	Core supply
VCC	29
VCC	45
VCC	48
VCC	49
VCC	57
VCC	87
VCC	101
VCC	114
VCC	123
VCC	137
VCC	143

4.2.1.18 Supply for I/O Cells: 3.3V nominal

Table 4-18 PGE Supply for I/O Cells: 3.3V nominal

Terminal		Signal Type	Reset Pull State	Pull Type	Description
Signal Name	144 PGE	Signal Type	Reset Pull State	Pull Type	Description
VCCIO	10	3.3-V Power	–	None	Operating supply for I/Os
VCCIO	26
VCCIO	42
VCCIO	104
VCCIO	120
VCCIO	136

4.2.1.19 Ground Reference for All Supplies Except VCCAD

Table 4-19 PGE Ground Reference for All Supplies Except VCCAD

Terminal		Signal Type	Reset Pull State	Pull Type	Description
Signal Name	144 PGE	Signal Type	Reset Pull State	Pull Type	Description
VSS	11	Ground	–	None	Ground reference
VSS	21
VSS	27
VSS	28
VSS	43
VSS	44
VSS	47
VSS	50
VSS	56
VSS	88
VSS	102
VSS	103
VSS	115
VSS	121
VSS	122
VSS	135
VSS	138
VSS	144

4.2.2 PZ Package Terminal Functions

4.2.2.1 High-End Timer (N2HET) Modules

Table 4-20 PZ Enhanced High-End Timer (N2HET) Modules

TERMINAL		SIGNAL TYPE	RESET PULL STATE	PULL TYPE	DESCRIPTION
SIGNAL NAME	100 PZ	SIGNAL TYPE	RESET PULL STATE	PULL TYPE	DESCRIPTION
N2HET1[0]/ SPI4CLK / EPWM2B	19	I/O	Pulldown	Programmable, 20 µA	N2HET2 timer input capture or output compare, or GIO. Each terminal has a suppression filter with a programmable duration. Timer input capture or output compare. The N2HET applicable terminals can be programmed as general-purpose input/output (GIO).
N2HET1[2] / SPI4SIMO / EPWM3A	22
N2HET1[4] / EPWM4B	25
N2HET1[6] / SCIRX / EPWM5A	26
N2HET1[8] / MIBSPI1SIMO[1]	74
N2HET1[10] / nTZ3	83
N2HET1[12]	89
N2HET1[14]	90
N2HET1[16] / EPWM1SYNCI / EPWM1SYNCO	97
MIBSPI1nCS[1] / N2HET1[17] / EQEP1S	93		Pullup
N2HET1[18] / EPWM6A	98		Pulldown
MIBSPI1nCS[2] / N2HET1[19]	27		Pullup
MIBSPI1nCS[3] / N2HET1[21]	39		Pullup
N2HET1[22]	11		Pulldown
MIBSPI1nENA / N2HET1[23] / ECAP4	68		Pullup
N2HET1[24] / MIBSPI1nCS[5]	64		Pulldown
MIBSPI3nENA / MIBSPI3nCS[5] / N2HET1[31] / EQEP1B	37		Pullup
GIOA[5] / INT[5] / EXTCLKIN /EPWM1A/N2HET1_PIN_nDIS	10		Pulldown		Disable selected PWM outputs
GIOA[2] / INT[2] / N2HET2[0] / EQEP2I	5		Pulldown		N2HET2 timer input capture or output compare, or GIO. Each terminal has a suppression filter with a programmable duration. Timer input capture or output compare. The N2HET applicable terminals can be programmed as general-purpose input/output (GIO).
GIOA[3] / INT[3] / N2HET2[2]	8
GIOA[6] / INT[6] / N2HET2[4] / EPWM1B	12
GIOA[7] / INT[7] / N2HET2[6] / EPWM2A	18

4.2.2.2 Enhanced Capture Modules (eCAP)

Table 4-21 PZ Enhanced Capture Modules (eCAP)

Terminal		Signal Type	Reset Pull State	Pull Type	Description
Signal Name	100 PZ	Signal Type	Reset Pull State	Pull Type	Description
MIBSPI3SOMI[0] / AWM1_EXT_ENA / ECAP2	34	I/O	Pullup	Fixed, 20 µA	Enhanced Capture Module 2 I/O
MIBSPI3SIMO[0] / AWM1_EXT_SEL[0] / ECAP3	35				Enhanced Capture Module 3 I/O
MIBSPI1NENA / N2HET1[23] / ECAP4	68				Enhanced Capture Module 4 I/O
MIBSPI1NCS[0] / MIBSPI1SOMI[1] / ECAP6	73				Enhanced Capture Module 6 I/O

4.2.2.3 Enhanced Quadrature Encoder Pulse Modules (eQEP)

Table 4-22 PZ Enhanced Quadrature Encoder Pulse Modules (eQEP)

TERMINAL		SIGNAL TYPE	RESET PULL STATE	PULL TYPE	DESCRIPTION
SIGNAL NAME	100 PZ	SIGNAL TYPE	RESET PULL STATE	PULL TYPE	DESCRIPTION
MIBSPI3CLK / AWM1_EXT_SEL[1] / EQEP1A	36	I/O	Pullup	Fixed, 20 µA	Enhanced QEP1 Input A
MIBSPI3nENA / MIBSPI3nCS[5] / N2HET1[31] / EQEP1B	37				Enhanced QEP1 Input B
MIBSPI3nCS[0] / AD2EVT / GIOB[2] / EQEP1I/N2HET2_PIN_nDIS	38				Enhanced QEP1 Index
MIBSPI1nCS[1] / N2HET1[17] / EQEP1S	93				Enhanced QEP1 Strobe
GIOA[2] / INT[2] / N2HET2[0] / EQEP2I	5		Pulldown		Enhanced QEP2 Index

4.2.2.4 Enhanced Pulse-Width Modulator Modules (ePWM)

Table 4-23 PZ Enhanced Pulse-Width Modulator Modules (ePWM)

TERMINAL		SIGNAL TYPE	RESET PULL STATE	PULL TYPE	DESCRIPTION
SIGNAL NAME	100 PZ	SIGNAL TYPE	RESET PULL STATE	PULL TYPE	DESCRIPTION
GIOA[5] / INT[5] / EXTCLKIN / EPWM1A/N2HET1_PIN_nDIS	10	Output	Pulldown	–	Enhanced PWM1 Output A
GIOA[6] / INT[6] / N2HET2[4] / EPWM1B	12	Output	Pulldown	–	Enhanced PWM1 Output B
N2HET1[16] / EPWM1SYNCI / EPWM1SYNCO	97	Input	Pulldown	Fixed, 20 µA	External ePWM Sync Pulse Input
N2HET1[16] / EPWM1SYNCI / EPWM1SYNCO	97	Output	Pulldown	–	External ePWM Sync Pulse Output
GIOA[7] / INT[7] / N2HET2[6] / EPWM2A	18				Enhanced PWM2 Output A
N2HET1[0] / SPI4CLK / EPWM2B	19				Enhanced PWM2 Output B
N2HET1[2] / SPI4SIMO / EPWM3A	22				Enhanced PWM3 Output A
N2HET1[4] / EPWM4B	25				Enhanced PWM4 Output B
N2HET1[6] / SCIRX / EPWM5A	26				Enhanced PWM5 Output A
N2HET1[18] / EPWM6A	98				Enhanced PWM6 Output A
N2HET1[10] / nTZ3	83	Input	Pulldown		Trip Zone 1 input 3

4.2.2.5 General-Purpose Input/Output (GIO)

Table 4-24 PZ General-Purpose Input/Output (GIO)

Terminal		Signal Type	Reset Pull State	Pull Type	Description
Signal Name	100 PZ	Signal Type	Reset Pull State	Pull Type	Description
GIOA
GIOA[0] / INT[0]	1	I/O	Pulldown	Programmable, 20 µA	General-purpose input/output All GPIO terminals are capable of generating interrupts to the CPU on rising/falling/both edges.
GIOA[1] / INT[1]	2
GIOA[2] / INT[2] / N2HET2[0] / EQEP2I	5
GIOA[3] / INT[3] / N2HET2[2]	8
GIOA[4]/ INT[4]	9
GIOA[5] / INT[5] / EXTCLKIN / EPWM1A/ N2HET1_PIN_nDIS	10
GIOA[6] / INT[6] / N2HET2[4] / EPWM1B	12
GIOA[7] / INT[7] / N2HET2[6] / EPWM2A	18
GIOB
MIBSPI3nCS[0] / AD2EVT / GIOB[2] / EQEP1I/N2HET2_PIN_nDIS	38	I/O			General-purpose input/output

4.2.2.6 Controller Area Network Interface Modules (DCAN1, DCAN2)

Table 4-25 PZ Controller Area Network Interface Modules (DCAN1, DCAN2)

Terminal		Signal Type	Reset Pull State	Pull Type	Description
Signal Name	100 PZ	Signal Type	Reset Pull State	Pull Type	Description
DCAN1
CAN1RX	63	I/O	Pullup	Programmable, 20 µA	CAN1 Receive, or general-purpose I/O (GPIO)
CAN1TX	62	I/O	Pullup	Programmable, 20 µA	CAN1 Transmit, or GPIO
DCAN2
CAN2RX	92	I/O	Pullup	Programmable, 20 µA	CAN2 Receive, or GPIO
CAN2TX	91	I/O	Pullup	Programmable, 20 µA	CAN2 Transmit, or GPIO

4.2.2.7 Standard Serial Peripheral Interfaces (SPI2 and SPI4)

Table 4-26 PZ Standard Serial Peripheral Interfaces (SPI2 and SPI4)

Terminal		Signal Type	Reset Pull State	Pull Type	Description
Signal Name	100 PZ	Signal Type	Reset Pull State	Pull Type	Description
SPI2
SPI2CLK	71	I/O	Pullup	Programmable, 20 µA	SPI2 Serial Clock, or GPIO
SPI2nCS[0]	23				SPI2 Chip Select, or GPIO
SPI2SIMO	70				SPI2 Slave-In-Master-Out, or GPIO
SPI2SOMI	69				SPI2 Slave-Out-Master-In, or GPIO
The drive strengths for the SPI2CLK, SPI2SIMO and SPI2SOMI signals are selected individually by configuring the respective SRS bits of the SPIPC9 register fo SPI2. SRS = 0 for 8mA drive (fast). This is the default mode as the SRS bits in the SPIPC9 register default to 0. SRS = 1 for 2mA drive (slow)
SPI4
N2HET1[0] / SPI4CLK / EPWM2B	19	I/O	Pulldown	Programmable, 20 µA	SPI2 Serial Clock, or GPIO
N2HET1[2] / SPI4SIMO / EPWM3A	22	I/O	Pulldown	Programmable, 20 µA	SPI2 Slave-In-Master-Out, or GPIO

4.2.2.8 Multibuffered Serial Peripheral Interface (MibSPI1 and MibSPI3)

Table 4-27 PZ Multibuffered Serial Peripheral Interface (MibSPI1 and MibSPI3)

Terminal		Signal Type	Reset Pull State	Pull Type	Description
Signal Name	100 PZ	Signal Type	Reset Pull State	Pull Type	Description
MibSPI1
MIBSPI1CLK	67	I/O	Pullup	Programmable, 20 µA	MibSPI1 Serial Clock, or GPIO
MIBSPI1nCS[0]/MIBSPI1SOMI[1]/ ECAP6	73				MibSPI1 Chip Select, or GPIO
MIBSPI1nCS[1]/N2HET1[17]/ EQEP1S	93
MIBSPI1nCS[2]/N2HET1[19]	27
MIBSPI1nCS[3]/N2HET1[21]	39
MIBSPI1nENA/N2HET1[23]/ ECAP4	68				MibSPI1 Enable, or GPIO
MIBSPI1SIMO[0]	65				MibSPI1 Slave-In-Master-Out, or GPIO
N2HET1[8]/MIBSPI1SIMO[1]	74				MibSPI1 Slave-In-Master-Out, or GPIO
MIBSPI1SOMI[0]	66				MibSPI1 Slave-Out-Master-In, or GPIO
MIBSPI1nCS[0]/MIBSPI1SOMI[1]/ ECAP6	73				MibSPI1 Slave-Out-Master-In, or GPIO
MibSPI3
MIBSPI3CLK/AWM1_EXT_SEL[1]/ EQEP1A	36	I/O	Pullup	Programmable, 20 µA	MibSPI3 Serial Clock, or GPIO
MIBSPI3nCS[0]/AD2EVT/GIOB[2]/ EQEP1I/N2HET2_PIN_nDIS	38				MibSPI3 Chip Select, or GPIO
MIBSPI3nENA/MIBSPI3nCS[5]/ N2HET1[31]/EQEP1B	37				MibSPI3 Chip Select, or GPIO
MIBSPI3nENA/MIBSPI3nCS[5]/ N2HET1[31]/EQEP1B	37				MibSPI3 Enable, or GPIO
MIBSPI3SIMO[0]/AWM1_EXT_SEL[0]/ ECAP3	35				MibSPI3 Slave-In-Master-Out, or GPIO
MIBSPI3SOMI[0]/AWM1_EXT_ENA/ ECAP2	34				MibSPI3 Slave-Out-Master-In, or GPIO

4.2.2.9 Local Interconnect Network Controller (LIN)

Table 4-28 PZ Local Interconnect Network Controller (LIN)

TERMINAL		SIGNAL TYPE	RESET PULL STATE	PULL TYPE	DESCRIPTION
SIGNAL NAME	100 PZ	SIGNAL TYPE	RESET PULL STATE	PULL TYPE	DESCRIPTION
LINRX	94	I/O	Pullup	Programmable, 20 µA	LIN Receive, or GPIO
LINTX	95	I/O	Pullup	Programmable, 20 µA	LIN Transmit, or GPIO

4.2.2.10 Multibuffered Analog-to-Digital Converter (MibADC)

Table 4-29 PZ Multibuffered Analog-to-Digital Converter (MibADC)

Terminal		Signal Type	Reset Pull State	Pull Type	Description
Signal Name	100 PZ	Signal Type	Reset Pull State	Pull Type	Description
MibADC1
AD1EVT	58	I/O	Pulldown	Programmable, 20 µA	ADC1 Event Trigger or GPIO
AD1IN[0]	42	Input	–	–	Analog Inputs
AD1IN[1]	49
AD1IN[2]	51
AD1IN[3]	52
AD1IN[4]	54
AD1IN[5]	55
AD1IN[6]	56
AD1IN[7]	43
AD1IN[8]/AD2IN[8]	57
AD1IN[9]/AD2IN[9]	48
AD1IN[10]/AD2IN[10]	50
AD1IN[11]/AD2IN[11]	53
AD1IN[16]/AD2IN[0]	40
AD1IN[17]/AD2IN[1]	41
AD1IN[20]/AD2IN[4]	44
AD1IN[21]/AD2IN[5]	45
ADREFHI/VCCAD	46	Input/ Power	–	–	ADC High Reference Level/ADC Operating Supply
ADREFLO/VSSAD	47	Input/ Ground	–	–	ADC Low Reference Level/ADC Supply Ground
MIBSPI3SOMI[0]/AWM1_EXT_ENA/ ECAP2	34				AWM external analog mux enable
MIBSPI3SIMO[0]/AWM1_EXT_SEL[0]/ ECAP3	35				AWM external analog mux select line 0
MIBSPI3CLK/AWM1_EXT_SEL[1]/ EQEP1A	36				AWM external analog mux select line1
MibADC2
MIBSPI3nCS[0]/AD2EVT/GIOB[2]/ EQEP1I/N2HET2_PIN_nDIS	38	I/O			ADC2 Event Trigger or GPIO

4.2.2.11 System Module Interface

Table 4-30 PZ System Module Interface

TERMINAL		SIGNAL TYPE	RESET PULL STATE	PULL TYPE	DESCRIPTION
SIGNAL NAME	100 PZ	SIGNAL TYPE	RESET PULL STATE	PULL TYPE	DESCRIPTION
nPORRST	31	Input	Pullup	100 µA	Power-on reset, cold reset External power supply monitor circuitry must drive nPORRST low when any of the supplies to the microcontroller fall out of the specified range. This terminal has a glitch filter. See Section 6.8.
nRST	81	I/O	Pullup	100 µA	The external circuitry can assert a system reset by driving nRST low. To ensure that an external reset is not arbitrarily generated, TI recommends that an external pullup resistor is connected to this terminal. This terminal has a glitch filter. See Section 6.8.
nERROR	82	I/O	Pulldown	20 µA	ESM Error Signal. Indicates error of high severity. See Section 6.8.

4.2.2.12 Clock Inputs and Outputs

Table 4-31 PZ Clock Inputs and Outputs

TERMINAL		SIGNAL TYPE	RESET PULL STATE	PULL TYPE	DESCRIPTION
SIGNAL NAME	100 PZ	SIGNAL TYPE	RESET PULL STATE	PULL TYPE	DESCRIPTION
OSCIN	14	Input	–	–	From external crystal/resonator, or external clock input
KELVIN_GND	15	Input	–	–	Dedicated ground for oscillator
OSCOUT	16	Output	–	–	To external crystal/resonator
ECLK	84	I/O	Pulldown	Programmable, 20 µA	External prescaled clock output, or GIO.
GIOA[5]/INT[5]/EXTCLKIN/EPWM1A/N2HET1_PIN_nDIS	10	Input	Pulldown	20 µA	External Clock In

4.2.2.13 Test and Debug Modules Interface

Table 4-32 PZ Test and Debug Modules Interface

TERMINAL		SIGNAL TYPE	RESET PULL STATE	PULL TYPE	DESCRIPTION
SIGNAL NAME	100 PZ	SIGNAL TYPE	RESET PULL STATE	PULL TYPE	DESCRIPTION
nTRST	76	Input	Pulldown	Fixed, 100 µA	JTAG test hardware reset
RTCK	80	Output	–	–	JTAG return test clock
TCK	79	Input	Pulldown	Fixed, 100 µA	JTAG test clock
TDI	77	I/O	Pullup	Fixed, 100 µA	JTAG test data in
TDO	78	I/O	Pulldown	Fixed, 100 µA	JTAG test data out
TMS	75	I/O	Pullup	Fixed, 100 µA	JTAG test select
TEST	24	I/O	Pulldown	Fixed, 100 µA	Test enable. This terminal must be connected to ground directly or via a pulldown resistor.

4.2.2.14 Flash Supply and Test Pads

Table 4-33 PZ Flash Supply and Test Pads

Terminal		Signal Type	Reset Pull State	Pull Type	Description
Signal Name	100 PZ	Signal Type	Reset Pull State	Pull Type	Description
VCCP	96	3.3-V Power	–	–	Flash external pump voltage (3.3 V). This terminal is required for both Flash read and Flash program and erase operations.
FLTP1	3	Input	–	–	Flash Test Pins. For proper operation this terminal must connect only to a test pad or not be connected at all [no connect (NC)]. The test pad must not be exposed in the final product where it might be subjected to an ESD event.
FLTP2	4	Input	–	–

4.2.2.15 Supply for Core Logic: 1.2-V Nominal

Table 4-34 PZ Supply for Core Logic: 1.2-V Nominal

Terminal		Signal Type	Reset Pull State	Pull Type	Description
Signal Name	100 PZ	Signal Type	Reset Pull State	Pull Type	Description
VCC	13	1.2-V Power	–	–	Digital logic and RAM supply
VCC	21
VCC	30
VCC	32
VCC	61
VCC	88
VCC	99

4.2.2.16 Supply for I/O Cells: 3.3-V Nominal

Table 4-35 PZ Supply for I/O Cells: 3.3-V Nominal

Terminal		Signal Type	Reset Pull State	Pull Type	Description
Signal Name	100 PZ	Signal Type	Reset Pull State	Pull Type	Description
VCCIO	6	3.3-V Power	–	–	I/O Supply
VCCIO	28
VCCIO	60
VCCIO	85

4.2.2.17 Ground Reference for All Supplies Except VCCAD

Table 4-36 PZ Ground Reference for All Supplies Except VCCAD

Terminal		Signal Type	Reset Pull State	Pull Type	Description
Signal Name	100 PZ	Signal Type	Reset Pull State	Pull Type	Description
VSS	7	Ground	–	–	Device Ground Reference. This is a single ground reference for all supplies except for the ADC Supply.
VSS	17
VSS	20
VSS	29
VSS	33
VSS	59
VSS	72
VSS	86
VSS	87
VSS	100

4.3 Pin Multiplexing

This microcontroller has several interfaces and uses extensive multiplexing to bring out the functions as required by the target application. The multiplexing is mostly on the output signals. A few inputs are also multiplexed to allow the same input signal to be driven in from a selected terminal.

4.3.1 Output Multiplexing

Table 4-37 and Table 4-38 show the pin multiplexing control x register (PINMMRx) and the associated bit fields that control each pin mux function.

Table 4-37 Multiplexing for Outputs on 144-Pin PGE Package⁽¹⁾

144-PIN PGE	DEFAULT FUNCTION	CTRL1	OPTION 2	CTRL2	OPTION 3	CTRL3	OPTION 4	CTRL4	OPTION 5	CTRL5	OPTION 6	CTRL6
86	AD1EVT	10[0]
2	GIOA[0]	0[8]
5	GIOA[1]	1[0]
9	GIOA[2]	2[0]					N2HET2[0]	2[3]	EQEP2I	2[4]
14	GIOA[5]	2[24]	EXTCLKIN1	2[25]	EPWM1A	2[26]
16	GIOA[6]	3[16]	N2HET2[4]	3[17]	EPWM1B	3[18]
22	GIOA[7]	4[0]	N2HET2[6]	4[1]	EPWM2A	4[2]
126	GIOB[0]	18[24]
133	GIOB[1]	21[8]
1	GIOB[3]	0[0]
105	MIBSPI1NCS[0]	13[24]	MIBSPI1SOMI[1]	13[25]					ECAP6	13[28]
130	MIBSPI1NCS[1]	20[16]	N2HET1[17]	20[17]					EQEP1S	20[20]
40	MIBSPI1NCS[2]	8[8]	N2HET1[19]	8[9]
96	MIBSPI1NENA	12[16]	N2HET1[23]	12[17]					ECAP4	12[20]
53	MIBSPI3CLK	33[24]	AWM1_EXT_SEL[1]	33[25]	EQEP1A	33[26]
55	MIBSPI3NCS[0]	9[16]	AD2EVT	9[17]	GIOB[2]	9[18]	EQEP1I	9[19]
37	MIBSPI3NCS[1]	7[8]	N2HET1[25]	7[9]
4	MIBSPI3NCS[2]	0[24]	I2C_SDA	0[25]	N2HET1[27]	0[26]	nTZ2	0[27]
3	MIBSPI3NCS[3]	0[16]	I2C_SCL	0[17]	N2HET1[29]	0[18]	nTZ1	0[19]
54	MIBSPI3NENA	9[8]	MIBSPI3NCS[5]	9[9]	N2HET1[31]	9[10]	EQEP1B	9[11]
52	MIBSPI3SIMO	33[16]	AWM1_EXT_SEL[0]	33[17]	ECAP3	33[18]
51	MIBSPI3SOMI	33[8]	AWM1_EXT_ENA	33[9]	ECAP2	33[10]
100	MIBSPI5CLK	13[16]
32	MIBSPI5NCS[0]	27[0]	EPWM4A	27[2]
97	MIBSPI5NENA	12[24]					MIBSPI5SOMI[1]	12[28]	ECAP5	12[29]
99	MIBSPI5SIMO[0]	13[8]					MIBSPI5SOMI[2]	13[12]
98	MIBSPI5SOMI[0]	13[0]
25	N2HET1[0]	5[0]	SPI4CLK	5[1]	EPWM2B	5[2]
23	N2HET1[01]	4[16]	SPI4NENA	4[17]				4[19]	N2HET2[8]	4[20]	EQEP2A	4[21]
30	N2HET1[02]	5[8]	SPI4SIMO	5[9]	EPWM3A	5[10]
24	N2HET1[03]	4[24]	SPI4NCS[0]	4[25]				4[27]	N2HET2[10]	4[28]	EQEP2B	4[29]
36	N2HET1[04]	33[0]	EPWM4B	33[1]
31	N2HET1[05]	5[16]	SPI4SOMI	5[17]	N2HET2[12]	5[18]	EPWM3B	5[19]
38	N2HET1[06]	7[16]	SCIRX	7[17]	EPWM5A	7[18]
33	N2HET1[07]	6[0]					N2HET2[14]	6[3]	EPWM7B	6[4]
106	N2HET1[08]	14[0]	MIBSPI1SIMO[1]	14[1]
35	N2HET1[09]	6[16]	N2HET2[16]	6[17]					EPWM7A	6[20]
118	N2HET1[10]	17[0]							nTZ3	17[4]
6	N2HET1[11]	1[8]	MIBSPI3NCS[4]	1[9]	N2HET2[18]	1[10]					EPWM1SYNCO	1[13]
124	N2HET1[12]	17[16]
39	N2HET1[13]	8[0]	SCITX	8[1]	EPWM5B	8[2]
125	N2HET1[14]	18[8]
41	N2HET1[15]	8[16]	MIBSPI1NCS[4]	8[17]	ECAP1	8[18]
139	N2HET1[16]	34[0]	EPWM1SYNCI	34[1]	EPWM1SYNCO	34[2]
140	N2HET1[18]	34[8]	EPWM6A	34[9]
141	N2HET1[20]	34[16]	EPWM6B	34[17]
15	N2HET1[22]	3[8]
91	N2HET1[24]	11[24]	MIBSPI1NCS[5]	11[25]
92	N2HET1[26]	12[0]
107	N2HET1[28]	14[8]
127	N2HET1[30]	19[8]					EQEP2S	19[11]

The CTRLx columns contain a value of type x[y], which indicates the pin multiplexing control x register (PINMMRx) and the associated bit field [y].

Table 4-38 Multiplexing for Outputs on 100-Pin PZ Package⁽¹⁾

100-PIN PZ	DEFAULT FUNCTION	CTRL1	OPTION 2	CTRL2	OPTION 3	CTRL3	OPTION 4	CTRL4	OPTION 5	CTRL5
2	GIOA[1]/INT[1]	1[0]
5	GIOA[2]/INT[2]	2[0]					N2HET2[0]	2[3]	EQEP2I	2[4]
10	GIOA[5]/INT[5]	2[24]	EXTCLKIN1	2[25]	EPWM1A	2[26]
12	GIOA[6]/INT[6]	3[16]	N2HET2[4]	3[17]	EPWM1B	3[18]
18	GIOA[7]/INT[7]	4[0]	N2HET2[6]	4[1]	EPWM2A	4[2]
73	MIBSPI1NCS[0]	13[24]	MIBSPI1SOMI[1]	13[25]					ECAP6	13[28]
93	MIBSPI1NCS[1]	20[16]	N2HET1[17]	20[17]					EQEP1S	20[20]
27	MIBSPI1NCS[2]	8[8]	N2HET1[19]	8[9]
68	MIBSPI1NENA	12[16]	N2HET1[23]	12[17]					ECAP4	12[20]
36	MIBSPI3CLK	33[24]	AWM1_EXT_SEL[1]	33[25]	EQEP1A	33[26]
38	MIBSPI3NCS[0]	9[16]	AD2EVT	9[17]	GIOB[2]	9[18]	EQEP1I	9[19]
37	MIBSPI3NENA	9[8]	MIBSPI3NCS[5]	9[9]	N2HET1[31]	9[10]	EQEP1B	9[11]
35	MIBSPI3SIMO[0]	33[16]	AWM1_EXT_SEL[0]	33[17]	ECAP3	33[18]
34	MIBSPI3SOMI[0]	33[8]	AWM1_EXT_ENA	33[9]	ECAP2	33[10]
19	N2HET1[0]	5[0]	SPI4CLK	5[1]	EPWM2B	5[2]
22	N2HET1[02]	5[8]	SPI4SIMO	5[9]	EPWM3A	5[10]
25	N2HET1[04]	33[0]	EPWM4B	33[1]
26	N2HET1[06]	7[16]	SCIRX	7[17]	EPWM5A	7[18]
74	N2HET1[08]	14[0]	MIBSPI1SIMO[1]	14[1]
83	N2HET1[10]	17[0]							nTZ3	17[4]
97	N2HET1[16]	34[0]	EPWM1SYNCI	34[1]	EPWM1SYNCO	34[2]
98	N2HET1[18]	34[8]	EPWM6A	34[9]
64	N2HET1[24]	11[24]	MIBSPI1NCS[5]	11[25]

(1) The CTRLx columns contain a value of type x[y], which indicates the pin multiplexing control x register (PINMMRx) and the associated bit field [y].

4.3.2 Multiplexing of Inputs

Some signals are connected to more than one terminal, the inputs for these signals can come from any of the terminals. A multiplexor is implemented to let the application choose the terminal that will be used, providing the input signal is from among the available options.

Table 4-39 Input Multiplexing and Control for All Packages [144-Pin PGE, and 100-Pin PZ]⁽¹⁾

SIGNAL NAME	DEDICATED INPUTS		MULTIPLEXED INPUTS		INPUT MULTIPLEXOR CONTROL		INPUT PATH SELECTED
SIGNAL NAME	144 PGE	100 PZ	144 PGE	100 PZ	BIT1	BIT2	DEDICATED, IF	MUXED, IF
GIOB[2]	142	–	55	38	PINMUX29[16]	PINMUX29[16]	BIT1 = 0⁽³⁾	BIT1 = 1⁽³⁾
N2HET1[17]	–	–	130	93	PINMUX20[17]	PINMUX24[16]	not(BIT1) or (BIT1 and BIT2) = 1	BIT1 and not(BIT2) = 1
N2HET1[19]	–	–	40	27	PINMUX8[9]	PINMUX24[24]	not(BIT1) or (BIT1 and BIT2) = 1	BIT1 and not(BIT2) = 1
N2HET1[21]	–	–	–	–	PINMUX9[25]	PINMUX25[0]	not(BIT1) or (BIT1 and BIT2) = 1	BIT1 and not(BIT2) = 1
N2HET1[23]	–	–	96	68	PINMUX12[17]	PINMUX25[8]	not(BIT1) or (BIT1 and BIT2) = 1	BIT1 and not(BIT2) = 1
N2HET1[25]	–	–	37	–	PINMUX7[9]	PINMUX25[16]	not(BIT1) or (BIT1 and BIT2) = 1	BIT1 and not(BIT2) = 1
N2HET1[27]	–	–	4	–	PINMUX0[26]	PINMUX25[24]	not(BIT1) or (BIT1 and BIT2) = 1	BIT1 and not(BIT2) = 1
N2HET1[29]	–	–	3	–	PINMUX0[18]	PINMUX26[0]	not(BIT1) or (BIT1 and BIT2) = 1	BIT1 and not(BIT2) = 1
N2HET1[31]	–	–	54	37	PINMUX9[10]	PINMUX26[8]	not(BIT1) or (BIT1 and BIT2) = 1	BIT1 and not(BIT2) = 1

The default inputs to the modules are from the dedicated input terminals. The application must configure the PINMUX registers as shown in order to select the multiplexed input path, if required.
The SPI4CLK, SPI4SIMO, SPI4SOMI, SPI4nENA and SPI4nCS[0] signals do not have a dedicated signal pad on this device. Therefore, the input multiplexors on these inputs are not required. The control registers are still available to maintain compatibility to the emulation device.
When the muxed input is selected for GIOB[2], the PINMUX9[16] and PINMUX9[17] must be cleared. These bits affect the control over the PULDIS (pull disable) and PSEL (pull select). When the multiplexed input path is selected for GIOB[2], the PULDIS is tied to 0 (pull is enabled, cannot be disabled) and the PULSEL is tied to 1 (pull up selected, not programmable).

4.4 Buffer Type

Table 4-40 Output Buffer Drive Strengths

Low-level Output Current, I_OL for V_I = V_OLmax or High-level Output Current, I_OH for V_I = V_OHmin	Signals
8mA	MIBSPI5CLK, MIBSPI5SOMI[0], MIBSPI5SOMI[1], MIBSPI5SOMI[2], MIBSPI5SOMI[3], MIBSPI5SIMO[0], MIBSPI5SIMO[1], MIBSPI5SIMO[2], MIBSPI5SIMO[3], TMS, TDI, TDO, RTCK, SPI4CLK, SPI4SIMO, SPI4SOMI, SPI4NCS[0], SPI4NENA, nERROR, N2HET2[1], N2HET2[3], N2HET2[5], N2HET2[7], N2HET2[9], N2HET2[11], N2HET2[13], N2HET2[15] ECAP1, ECAP4, ECAP5, ECAP6 EQEP1I, EQEP1S, EQEP2I, EQEP2S EPWM1A, EPWM1B, EPWM1SYNCO, EPW2A, EPWM2B, EPWM3A, EPWM3B, EPWM4A, EPWM4B, EPWM5A, EPWM5B, EPWM6A, EPWM6B, EPWM7A, EPWM7B
4mA	TEST, MIBSPI3SOMI, MIBSPI3SIMO, MIBSPI3CLK, MIBSPI1SIMO, MIBSPI1SOMI, MIBSPI1CLK, ECAP2, ECAP3 nRST
2mA zero-dominant	AD1EVT, CAN1RX, CAN1TX, CAN2RX, CAN2TX, CAN3RX, CAN3TX, GIOA[0-7], GIOB[0-7], LINRX, LINTX, MIBSPI1NCS[0], MIBSPI1NCS[1-3], MIBSPI1NENA, MIBSPI3NCS[0-3], MIBSPI3NENA, MIBSPI5NCS[0-3], MIBSPI5NENA, N2HET1[0-31], N2HET2[0], N2HET2[2], N2HET2[4], N2HET2[6], N2HET2[8], N2HET2[10], N2HET2[12], N2HET2[14], N2HET2[16], N2HET2[18],
selectable 8mA / 2mA	ECLK, SPI2CLK, SPI2SIMO, SPI2SOMI The default output buffer drive strength is 8mA for these signals.

Table 4-41 Selectable 8mA/2mA Control

SIGNAL	CONTROL BIT	ADDRESS	2mA
ECLK	SYSPC10[0]	0xFFFF FF78	1
SPI2CLK	SPI2PC9[9]	0xFFF7 F668	1
SPI2SIMO	SPI2PC9[10]	0xFFF7 F668	1
SPI2SOMI	SPI2PC9[11]⁽¹⁾	0xFFF7 F668	1

(1) Either SPI2PC9[11] or SPI2PC9[24] can change the output strength of the SPI2SOMI pin. In case of a 32-bit write where these two bits differ, SPI2PC9[11] determines the drive strength.