SPRABJ8B September   2022  – November 2023 AM2631 , AM2631-Q1 , AM2632 , AM2632-Q1 , AM2634 , AM2634-Q1 , AM263P2 , AM263P4 , AM263P4-Q1

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1 Introduction
    1. 1.1 Acronyms
  5. 2 Power
    1. 2.1 Discrete DC-DC Power Solution
    2. 2.2 Integrated PMIC Power Solution
    3. 2.3 Power Decoupling and Filtering
    4. 2.4 Power Consumption
    5. 2.5 Power Distribution Network
      1. 2.5.1 Simulations
        1. 2.5.1.1 Core Digital Power 1.2 V
        2. 2.5.1.2 Digital/Analog I/O Power 3.3 V
    6. 2.6 e-Fuse Power
  6. 3 Clocking
    1. 3.1 Crystal and Oscillator Input Options
    2. 3.2 Output Clock Generation
    3. 3.3 Crystal Selection and Shunt Capacitance
    4. 3.4 Crystal Placement and Routing
  7. 4 Resets
  8. 5 Bootstrapping
    1. 5.1 SOP Signal Implementation
    2. 5.2 OSPI/QSPI Memory Implementation
    3. 5.3 ROM OSPI/QSPI Boot Requirements
  9. 6 JTAG Emulators and Trace
  10. 7 Multiplexed Peripherals
  11. 8 Digital Peripherals
    1. 8.1 General Digital Peripheral Routing Guidelines
  12. 9 Analog Peripherals
    1. 9.1 General Analog Peripheral Routing Guidelines
      1. 9.1.1 Resolver ADC Routing Guidelines
  13. 10Layer Stackup
    1. 10.1 Key Stackup Features
  14. 11Vias
  15. 12BGA Power Fan-Out and Decoupling Placement
    1. 12.1 Ground Return
    2. 12.2 1.2 V Core Digital Power
      1. 12.2.1 Key Layout Considerations
    3. 12.3 3.3 V Digital and Analog Power
      1. 12.3.1 Key Layout Considerations
    4. 12.4 1.8 V Digital and Analog Power
      1. 12.4.1 Key Layout Considerations
  16. 13References
  17.   Revision History

5.1 SOP Signal Implementation

Each SOP bootmode selection signal is multiplexed with a subset of OSPI/QSPI and SPI peripheral functional mode signals. For all signal descriptions, see the Signal Description tables in the AM263x Sitara™ Microcontroller Data Sheet and AM263Px Sitara™ Microcontroller Data Sheet. The SOP signal descriptions are excerpted in Figure 5-1.

Table 5-1 SOP and Functional Mode Signal Mapping
AM263x/AM263Px Pin Number Primary Pinmux Signal SOP Mode Signal
N1 OSPI0/QSPI0_D0 SOP[0]
N4 OSPI0/QSPI_D1 SOP[1]
A11 SPI0_CLK SOP[2]
C10 SPI0_D0 SOP[3]

Because of this SOP/functional-mode multiplexing additional care must be taken in schematic and layout to ensure that the SOP mode selection resistors, jumpers or switch paths are routed in such a way that the SOP mode branches do not present inductive stubs to the functional mode signal paths. Failing to take care of this may result in non-functional OSPI/QSPI or SPI interfaces.

GUID-20220808-SS0I-M9WB-WBWX-WCXKGR5WNDSQ-low.svg Figure 5-1 Excerpt From AM263x Launchpad Schematic – SOP[3:0] Functional and SOP Paths

In the AM263x and AM263Px Control Card and Launchpad designs this SOP mode isolation is accomplished by including a 10KΩ resistor in the SOP signal path. The resistor is placed such as one pad is as close to the AM263x BGA pad and in-line with the functional mode path. This creates a layout where the additional stub length necessary to breakout the SOP path will only minimally impact the functional mode operation of the signals, as shown in Figure 5-2 and Figure 5-3.

GUID-20220808-SS0I-TPHJ-4TPV-TMLN1N96KL5J-low.png Figure 5-2 Excerpt From AM263x Launchpad Layout – All SOP[3:0] Functional and SOP Paths
GUID-20220808-SS0I-02RC-2J9W-GC6K4N5ZF9WF-low.png Figure 5-3 Excerpt From AM263x Launchpad Layout – Highlighting SOP0/QSPI_D0 Path and SOP Isolation Resistor