SPRAC71B February   2019  – October 2023

 

  1.   1
  2. 1 Introduction
    1. 1.1  ABIs for the C28x
    2. 1.2  Scope
    3. 1.3  ABI Variants
    4. 1.4  Toolchains and Interoperability
    5. 1.5  Libraries
    6. 1.6  Types of Object Files
    7. 1.7  Segments
    8. 1.8  C28x Architecture Overview
    9. 1.9  C28x Memory Models
    10. 1.10 Reference Documents
    11. 1.11 Code Fragment Notation
  3. 2 Data Representation
    1. 2.1 Basic Types
    2. 2.2 Data in Registers
    3. 2.3 Data in Memory
    4. 2.4 Pointer Types
    5. 2.5 Complex Types
    6. 2.6 Structures and Unions
    7. 2.7 Arrays
    8. 2.8 Bit Fields
      1. 2.8.1 Volatile Bit Fields
    9. 2.9 Enumeration Types
  4. 3 Calling Conventions
    1. 3.1 Call and Return
      1. 3.1.1 Call Instructions
        1. 3.1.1.1 Indirect Calls
        2. 3.1.1.2 Direct Calls
      2. 3.1.2 Return Instruction
      3. 3.1.3 Pipeline Conventions
      4. 3.1.4 Weak Functions
    2. 3.2 Register Conventions
      1. 3.2.1 Argument Registers
      2. 3.2.2 Callee-Saved Registers
    3. 3.3 Argument Passing
      1. 3.3.1 Passing 16-Bit Arguments
      2. 3.3.2 Passing Longer Arguments
      3. 3.3.3 C++ Argument Passing
      4. 3.3.4 Passing Structs and Unions
      5. 3.3.5 Stack Layout of Arguments Not Passed in Registers
      6. 3.3.6 Frame Pointer
    4. 3.4 Return Values
    5. 3.5 Structures and Unions Passed and Returned by Reference
    6. 3.6 Conventions for Compiler Helper Functions
    7. 3.7 Prolog and Epilog Helper Functions
    8. 3.8 Scratch Registers for Functions Already Seen
    9. 3.9 Interrupt Functions
  5. 4 Data Allocation and Addressing
    1. 4.1 Data Sections and Segments
    2. 4.2 Data Blocking
    3. 4.3 Addressing Modes
    4. 4.4 Allocation and Addressing of Static Data
      1. 4.4.1 Addressing Methods for Static Data
      2. 4.4.2 Placement Conventions for Static Data
        1. 4.4.2.1 Abstract Conventions for Addressing
      3. 4.4.3 Initialization of Static Data
    5. 4.5 Automatic Variables
    6. 4.6 Frame Layout
      1. 4.6.1 Stack Alignment
      2. 4.6.2 Register Save Order
    7. 4.7 Heap-Allocated Objects
  6. 5 Code Allocation and Addressing
    1. 5.1 Computing the Address of a Code Label
    2. 5.2 Calls
      1. 5.2.1 Direct Call
      2. 5.2.2 Far Call Trampoline
      3. 5.2.3 Indirect Calls
  7. 6 Helper Function API
    1. 6.1 Floating-Point Behavior
    2. 6.2 C Helper Function API
    3. 6.3 Floating-Point Helper Functions for C99
  8. 7 Standard C Library API
    1. 7.1  About Standard C Libraries
    2. 7.2  Reserved Symbols
    3. 7.3  <assert.h> Implementation
    4. 7.4  <complex.h> Implementation
    5. 7.5  <ctype.h> Implementation
    6. 7.6  <errno.h> Implementation
    7. 7.7  <float.h> Implementation
    8. 7.8  <inttypes.h> Implementation
    9. 7.9  <iso646.h> Implementation
    10. 7.10 <limits.h> Implementation
    11. 7.11 <locale.h> Implementation
    12. 7.12 <math.h> Implementation
    13. 7.13 <setjmp.h> Implementation
    14. 7.14 <signal.h> Implementation
    15. 7.15 <stdarg.h> Implementation
    16. 7.16 <stdbool.h> Implementation
    17. 7.17 <stddef.h> Implementation
    18. 7.18 <stdint.h> Implementation
    19. 7.19 <stdio.h> Implementation
    20. 7.20 <stdlib.h> Implementation
    21. 7.21 <string.h> Implementation
    22. 7.22 <tgmath.h> Implementation
    23. 7.23 <time.h> Implementation
    24. 7.24 <wchar.h> Implementation
    25. 7.25 <wctype.h> Implementation
  9. 8 C++ ABI
    1. 8.1  Limits (GC++ABI 1.2)
    2. 8.2  Export Template (GC++ABI 1.4.2)
    3. 8.3  Data Layout (GC++ABI Chapter 2)
    4. 8.4  Initialization Guard Variables (GC++ABI 2.8)
    5. 8.5  Constructor Return Value (GC++ABI 3.1.5)
    6. 8.6  One-Time Construction API (GC++ABI 3.3.2)
    7. 8.7  Controlling Object Construction Order (GC++ ABI 3.3.4)
    8. 8.8  Demangler API (GC++ABI 3.4)
    9. 8.9  Static Data (GC++ ABI 5.2.2)
    10. 8.10 Virtual Tables and the Key function (GC++ABI 5.2.3)
    11. 8.11 Unwind Table Location (GC++ABI 5.3)
  10. 9 Exception Handling
    1. 9.1  Overview
    2. 9.2  PREL31 Encoding
    3. 9.3  The Exception Index Table (EXIDX)
      1. 9.3.1 Pointer to Out-of-Line EXTAB Entry
      2. 9.3.2 EXIDX_CANTUNWIND
      3. 9.3.3 Inlined EXTAB Entry
    4. 9.4  The Exception Handling Instruction Table (EXTAB)
      1. 9.4.1 EXTAB Generic Model
      2. 9.4.2 EXTAB Compact Model
      3. 9.4.3 Personality Routines
    5. 9.5  Unwinding Instructions
      1. 9.5.1 Common Sequence
      2. 9.5.2 Byte-Encoded Unwinding Instructions
    6. 9.6  Descriptors
      1. 9.6.1 Encoding of Type Identifiers
      2. 9.6.2 Scope
      3. 9.6.3 Cleanup Descriptor
      4. 9.6.4 Catch Descriptor
      5. 9.6.5 Function Exception Specification (FESPEC) Descriptor
    7. 9.7  Special Sections
    8. 9.8  Interaction With Non-C++ Code
      1. 9.8.1 Automatic EXIDX Entry Generation
      2. 9.8.2 Hand-Coded Assembly Functions
    9. 9.9  Interaction With System Features
      1. 9.9.1 Shared Libraries
      2. 9.9.2 Overlays
      3. 9.9.3 Interrupts
    10. 9.10 Assembly Language Operators in the TI Toolchain
  11. 10DWARF
    1. 10.1 DWARF Register Names
    2. 10.2 Call Frame Information
    3. 10.3 Vendor Names
    4. 10.4 Vendor Extensions
  12. 11ELF Object Files (Processor Supplement)
    1. 11.1 Registered Vendor Names
    2. 11.2 ELF Header
    3. 11.3 Sections
      1. 11.3.1 Section Indexes
      2. 11.3.2 Section Types
      3. 11.3.3 Extended Section Header Attributes
      4. 11.3.4 Subsections
      5. 11.3.5 Special Sections
      6. 11.3.6 Section Alignment
    4. 11.4 Symbol Table
      1. 11.4.1 Symbol Types
      2. 11.4.2 Common Block Symbols
      3. 11.4.3 Symbol Names
      4. 11.4.4 Reserved Symbol Names
      5. 11.4.5 Mapping Symbols
    5. 11.5 Relocation
      1. 11.5.1 Relocation Types
        1. 11.5.1.1 Absolute Relocations
        2. 11.5.1.2 PC-Relative Relocations
        3. 11.5.1.3 Relocations in Data Sections
        4. 11.5.1.4 Relocations for C28x Instructions
        5. 11.5.1.5 Other Relocation Types
      2. 11.5.2 Relocation Operations
      3. 11.5.3 Relocation of Unresolved Weak References
  13. 12ELF Program Loading and Linking (Processor Supplement)
    1. 12.1 Program Header
      1. 12.1.1 Base Address
      2. 12.1.2 Segment Contents
      3. 12.1.3 Thread-Local Storage
    2. 12.2 Program Loading
  14. 13Build Attributes
    1. 13.1 About Build Attributes
    2. 13.2 C28x ABI Build Attribute Subsection
    3. 13.3 Build Attribute Tags
  15. 14Copy Tables and Variable Initialization
    1. 14.1 About Copy Tables
    2. 14.2 Copy Table Format
    3. 14.3 Compressed Data Formats
      1. 14.3.1 RLE
      2. 14.3.2 LZSS Format
    4. 14.4 Variable Initialization
  16. 15Revision History
    1.     188

3.2 Register Conventions

Implementations must not use the special-purpose registers for any purpose other than the dedicated special purpose. The remaining registers are general-purpose registers.

SP is the call stack pointer. The stack pointer must always remain properly aligned, even during hand-coded assembly functions (see Section 4.6.1). TMS320C28x requires alignment to 16-bit words. Stack management and the local frame structure is presented in Section 4.6.

The ABI designates the following as callee-saved registers. That is, a called function is expected to preserve them so they have the same value on return from a function as they had at the point of the call.

  • XAR1-XAR3
  • R4H-R7H (on FPU32)
  • R4L-R7L (on FPU64)

All other registers are caller-save registers. That is, they are not preserved across a call, so if their value is needed following the call, the caller is responsible for saving and restoring their contents.

Table 3-1 TMS320C28x Register Conventions
RegisterSizeDescription
ACC32 bitsAccumulator
AH16 bitsHigh half of ACC
AL16 bitsLow half of ACC
XAR016 bitsAuxiliary register 0
XAR132 bitsAuxiliary register 1
XAR232 bitsAuxiliary register 2
XAR332 bitsAuxiliary register 3
XAR432 bitsAuxiliary register 4
XAR532 bitsAuxiliary register 5
XAR632 bitsAuxiliary register 6
XAR732 bitsAuxiliary register 7
AR016 bitsLow half of XAR0
AR116 bitsLow half of XAR1
AR216 bitsLow half of XAR2
AR316 bitsLow half of XAR3
AR416 bitsLow half of XAR4
AR516 bitsLow half of XAR5
AR616 bitsLow half of XAR6
AR716 bitsLow half of XAR7
DP16 bits         Data-page pointer              
IFR16 bitsInterrupt flag register
IER16 bitsInterrupt enable register
DBGIER16 bitsDebug interrupt enable register
P32 bitsProduct register
PH16 bitsHigh half of P
PL16 bitsLow half of P
PC22 bitsProgram counter
RPC22 bitsReturn program counte
SP16 bitsStack pointer
ST016 bitsStatus register 0
ST116 bitsStatus register 1
XT32 bitsMultiplicand register
T16 bitsHigh half of XT
TL16 bitsLow half of XT

In addition, some devices have an FPU instruction set, which adds registers R0-R7.

Figure 3-1 shows the C28x registers. See the TMS320C28x DSP CPU and Instruction Set Reference Guide (SPRU430) for more information about the registers.

GUID-533B5920-8B5C-4E28-845E-42DDED3B58E9-low.gifFigure 3-1 C28x Registers