SPRAC76G November   2022  – February 2024 AM5706 , AM5708 , AM5716 , AM5718 , AM5726 , AM5728 , AM5729 , AM5746 , AM5748 , AM5749 , AM620-Q1 , AM623 , AM625 , AM625-Q1 , AM625SIP , AM6411 , AM6412 , AM6421 , AM6422 , AM6441 , AM6442 , AM6526 , AM6528 , AM6546 , AM6548

 

  1.   1
  2.   Sitara Processor Power Distribution Networks: Implementation and Analysis
  3.   Trademarks
  4. 1Introduction
    1. 1.1 Acronyms Used in This Document
  5. 2Guidelines for PCB Stack-Up
  6. 3Physical Layout Optimization of the PDN
  7. 4Static PDN Analysis (IR Drop Optimization)
  8. 5Dynamic Analysis of PCB PDN
    1. 5.1 Selecting Decoupling Capacitors to Meet ZTARGET
  9. 6Checklist for PDN
  10. 7Implementation Examples and PDN Targets
    1. 7.1 AM570x
    2. 7.2 AM571x
    3. 7.3 AM572x
    4. 7.4 AM574x
    5. 7.5 AM65xx/DRA80xM
    6. 7.6 AM62xx
    7. 7.7 AM64xx
    8. 7.8 AM62Ax
  11.   Revision History

7.3 AM572x

GUID-15B865AE-A87A-4A97-8296-8928A2D00D6B-low.gif
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Table 7-3 AM572x PDN Targets and Decoupling Example
Supply
Name(10)		Static
PDN
Target		Dynamic PDN TargetsNumber of Decoupling
Capacitors Per Supply (1)(2)(3)(4)(5)(6) (9)
Max Reff
(mΩ) (7)		Dec Cap
Max LL
(nH) (6)(8)		Max
Impedance
(mΩ)		Frequency
of Interest
(MHz)		100
nF		220
nF		470
nF		1
µF		2.2
µF		4.7
µF		10
µF		22
µF
VDD_CORE27287≤50611111
VDD_MPU10257≤2012223111
VDD_DSPEVE132.554≤208112111
VDD_IVA482800≤100511
VDD_GPU182.5207≤50611111
VDDS_DDR1102.5200≤10084221
VDDS_DDR2102.5200≤10084221
CAP_VBBLDO_DSPEVEN/A6N/AN/A1
CAP_VBBLDO_GPUN/A6N/AN/A1
CAP_VBBDLO_IVAN/A6N/AN/A1
CAP_VBBLD0_MPUN/A6N/AN/A1
CAP_VDDRAM_CORE1N/A6N/AN/A1
CAP_VDDRAM_CORE2N/A6N/AN/A1
CAP_VDDRAM_CORE3N/A6N/AN/A1
CAP_VDDRAM_CORE4N/A6N/AN/A1
CAP_VDDRAM_CORE5N/A6N/AN/A1
CAP_VDDRAM_DSPEVE1N/A6N/AN/A1
CAP_VDDRAM_DSPEVE2N/A6N/AN/A1
CAP_VDDRAM_GPUN/A6N/AN/A1
CAP_VDDRAM_IVAN/A6N/AN/A1
CAP_VDDRAM_MPU1N/A6N/AN/A1
CAP_VDDRAM_MPU2N/A6N/AN/A
(1) For more information on peak-to-peak noise values, see the Recommended Operating Conditions table in the device-specific data manual.
(2) ESL must be as low as possible and not exceed 0.5 nH.
(3) The power delivery network (PDN) impedance characteristics are defined versus the device activity (that runs at different frequency) based on the Recommended Operating Conditions table in the Specifications chapter of the device-specific data manual.
(4) The static drop requirement drives the maximum acceptable PCB resistance between the PMIC or the external SMPS and the processor power balls.
(5) Assuming that the external SMPS (power IC) feedback sense is taken close to processor power balls.
(6) High-frequency (30 MHz – 70 MHz) PCB decoupling capacitors.
(7) Maximum Reff from VRM/SMPS/PMIC to processor.
(8) Maximum loop inductance for decoupling capacitor.
(9) Decoupling capacitor counts and values are provided as a baseline recommendation only. TI recommends that all PCB designs be simulated prior fabrication to ensure that the processor PDN requirements are met.
(10) Ganged rails must meet all requirements of each member rail.