SPRAC77E January   2022  – February 2022 TMS320F28379D , TMS320F28379D-Q1 , TMS320F28379S

 

  1.   Trademarks
  2. 1Introduction
  3. 2PTO – PulseGen
    1. 2.1 PulseGen Implementation Overview
    2. 2.2 PulseGen Limitations
    3. 2.3 PulseGen CLB Configuration
    4. 2.4 PulseGen Input and Output Signals
  4. 3PTO – QepDiv
    1. 3.1 QepDiv Implementation Overview
    2. 3.2 QepDiv Limitations
    3. 3.3 QepDiv Divider Settings and Initialization
    4. 3.4 QepDiv CLB Configuration
  5. 4PTO – Abs2Qep
    1. 4.1 Abs2Qep Chip resources
    2. 4.2 Abs2Qep Theory of Operation
      1. 4.2.1 Abs2Qep Translation Equations
      2. 4.2.2 Abs2Qep Translation Example
      3. 4.2.3 Abs2Qep Zero Cross Detection
    3. 4.3 Abs2Qep CLB Configuration
      1. 4.3.1 Abs2Qep QEP-A/B Pulse Train Generation
      2. 4.3.2 Abs2Qep Halt Latch
      3. 4.3.3 Abs2Qep High Level Controller (HLC)
    4. 4.4 Abs2Qep Input and Output Signals
  6. 5PTO – QepOnClb QEP Decoder
    1. 5.1 QepOnClb and eQEP Comparison
    2. 5.2 QepOnClb Chip resources
    3. 5.3 QepOnClb Theory of Operation
    4. 5.4 QepOnClb CLB Resources
      1. 5.4.1 QepOnClb QCLK State Machine
      2. 5.4.2 QepOnClb Direction Decode
      3. 5.4.3 QepOnClb Error Detection
      4. 5.4.4 QepOnClb Simulation Waveforms
  7. 6Example Projects
    1. 6.1 Hardware Requirements
    2. 6.2 Installing Code Composer Studio and C2000WARE-MOTORCONTROL-SDK™
    3. 6.3 Import and Run Example Project
    4. 6.4 PulseGen Example
    5. 6.5 QepDiv Example
    6. 6.6 Abs2Qep Example
      1. 6.6.1 Watch Variables
      2. 6.6.2 Test Signals
      3. 6.6.3 Pin Usage and Test Connections
    7. 6.7 QepOnClb Example
      1. 6.7.1 Watch Variables
      2. 6.7.2 Header Pin Connections
  8. 7Library Source and Projects
    1. 7.1 Locating the Library Source Code
    2. 7.2 Import and Build the Library Project
    3. 7.3 PTO - PulseGen API
      1. 7.3.1 pto_pulsegen_runPulseGen
      2. 7.3.2 pto_startOperation
      3. 7.3.3 pto_pulsegen_setupPeriph
      4. 7.3.4 pto_pulsegen_reset
    4. 7.4 PTO - QepDiv API
      1. 7.4.1 pto_qepdiv_config
      2. 7.4.2 pto_startOperation
      3. 7.4.3 pto_qepdiv_setupPeriph
      4. 7.4.4 pto_qepdiv_reset
    5. 7.5 PTO - Abs2Qep API
      1. 7.5.1 Abs2Qep API Configuration
      2. 7.5.2 pto_abs2qep_runPulseGen
      3. 7.5.3 pto_abs2qep_setupPeriph
      4. 7.5.4 pto_abs2qep_translatePosition
    6. 7.6 PTO - QepOnClb API
      1. 7.6.1 pto_qeponclb_setupPeriph
      2. 7.6.2 pto_qeponclb_initCLBQEP
      3. 7.6.3 pto_qeponclb_configMaxCounterPos
      4. 7.6.4 pto_qeponclb_enableCLBQEP
      5. 7.6.5 pto_qeponclb_resetCLBQEP
      6. 7.6.6 pto_qeponclb_getCounterVal
      7. 7.6.7 pto_qeponclb_getCLBQEPPos
      8. 7.6.8 pto_qeponclb_clearFIFOptr
  9. 8Using the Reference APIs in Projects
    1. 8.1 Adding PTO Support to a Project
    2. 8.2 Routing To and From the CLB
    3. 8.3 Initialization Steps
      1. 8.3.1 PTO-PulseGen API Initalization
      2. 8.3.2 PTO-QepDiv API Initialization
      3. 8.3.3 PTO-Abs2Qep API Initialization
      4. 8.3.4 PTO-QepOnClb API Initialization
  10. 9References
  11.   Revision History

5.4 QepOnClb CLB Resources

The decoder CLB configuration is shown in Figure 5-4 and further described in Table 5-3.

Figure 5-4 QepOnClb Tile Block Diagram
Table 5-3 QepOnClb Tile 1
Resource Function Notes
Inputs
In0 QEP_RESET Connected to GPREG bit 0 for software control of the position counter reset.
  • 1: Reset the position counter. The counter will remain in reset until a 0 is written to this bit.
  • 0: Release the counter from reset. The position counter will increment / decrement as required if QEP_ENABLE is 1.
In1 QEP-I As designed, the rising edge of this signal will prompt the HLC to store the current position counter in the FIFO. This is similar to the eQEP latch on rising edge mode.
In2 QEP_ENABLE Connected to GPREG bit 2. Provides an position counter enable/disable switch from software.
  • 1: QEP is enabled. The position counter will increment / decrement as required if the reset signal, QEP_RESET, is also 0.
  • 0: QEP is disabled. The position counter stops incrementing / decrementing.
In3 QEP-A The state transitions of QEP-A and QEP-B are used to detect movement, direction of the movement, or an error.
In4 Not used Not used
In5 QEP-B The state transitions of QEP-A and QEP-B are used to detect movement, direction of the movement, or an error.
In6 Not used Not used
In7 Not used Not used
Outputs
Out0 Not used Not used
Out1 Not used Not used
Out2 Not used Not used
Out3 Not used Not used
Out4 Not used Not used
Out5 Not used Not used
Out6 Not used Not used
Out7 Not used Not used
Logic Resources
LUT0 Count direction control Determines the direction of movement. Decodes the phase by comparing the current QEP-A, QEP-B state to the previous state. The output sets the position counter's mode appropriately.
  • QEP-A leads (forward): DIRECTION is 1 and the position counter mode is increment.
  • QEP-A lags (reverse): DIRECTION is 0 and the position counter mode is decrement.
LUT1 Count enable control Enables the position counter to increment, or decrement, by one. This occurs when both of these conditions are met:
  1. QEP_ENABLE is 1 and
  2. QCLK is 1
LUT2 QEP reset generation Resets the position counter when either of these conditions are met:
  1. QEP_RESET is 1 or
  2. The position counter match2 is asserted
FSM0 QCLK state machine This FSM has two functions:
  • Monitors the QEP-A/B signals to detect a valid state change. This change will pull QCLK high which will allow the position counter to increment or decrement. Refer to LUT1.
  • Stores the previous QEP-A/B levels. The previous state is used to detect the direction of movement or an error. Refer to LUT0 and FSM1.
FSM1 Error detection Compares the previous QEP-A/B state with the current state. If both signals changed at the same time, then the internal ERROR signal is forced high. As designed, the rising-edge of ERROR will trigger the HLC to send an interrupt with Tag 11.
FSM2 Not used Not used
CNT0 Position counter If enabled (QCLK is 1) increment or decrement by one on each CLB clock cycle. The position counter's maximum position (MAXPOS) is specified by the following:
  • load: Maximum position minus 1 (MAXPOS - 1). This value is loaded into the counter when an event is triggered by match2.
  • match1: Maximum position (MAXPOS) resets the counter when reached.
  • match2: 0xFFFFFFFF triggers a counter event which loads the counter with the load value.
CNT1 Not used Not used
CNT2 Not used Not used
High Level Controller
HLC Event 0: Error detected. Sent an error interrupt to the CPU with Tag 11.
Event 3: Counter capture Responds to the QEP-I rising edge by copying the current position counter to the FIFO. The HLC then interrupts the CPU and Tag 5 is set.