SPRAC77E January   2022  – February 2022 TMS320F28379D , TMS320F28379D-Q1 , TMS320F28379S

 

  1.   Trademarks
  2. 1Introduction
  3. 2PTO – PulseGen
    1. 2.1 PulseGen Implementation Overview
    2. 2.2 PulseGen Limitations
    3. 2.3 PulseGen CLB Configuration
    4. 2.4 PulseGen Input and Output Signals
  4. 3PTO – QepDiv
    1. 3.1 QepDiv Implementation Overview
    2. 3.2 QepDiv Limitations
    3. 3.3 QepDiv Divider Settings and Initialization
    4. 3.4 QepDiv CLB Configuration
  5. 4PTO – Abs2Qep
    1. 4.1 Abs2Qep Chip resources
    2. 4.2 Abs2Qep Theory of Operation
      1. 4.2.1 Abs2Qep Translation Equations
      2. 4.2.2 Abs2Qep Translation Example
      3. 4.2.3 Abs2Qep Zero Cross Detection
    3. 4.3 Abs2Qep CLB Configuration
      1. 4.3.1 Abs2Qep QEP-A/B Pulse Train Generation
      2. 4.3.2 Abs2Qep Halt Latch
      3. 4.3.3 Abs2Qep High Level Controller (HLC)
    4. 4.4 Abs2Qep Input and Output Signals
  6. 5PTO – QepOnClb QEP Decoder
    1. 5.1 QepOnClb and eQEP Comparison
    2. 5.2 QepOnClb Chip resources
    3. 5.3 QepOnClb Theory of Operation
    4. 5.4 QepOnClb CLB Resources
      1. 5.4.1 QepOnClb QCLK State Machine
      2. 5.4.2 QepOnClb Direction Decode
      3. 5.4.3 QepOnClb Error Detection
      4. 5.4.4 QepOnClb Simulation Waveforms
  7. 6Example Projects
    1. 6.1 Hardware Requirements
    2. 6.2 Installing Code Composer Studio and C2000WARE-MOTORCONTROL-SDK™
    3. 6.3 Import and Run Example Project
    4. 6.4 PulseGen Example
    5. 6.5 QepDiv Example
    6. 6.6 Abs2Qep Example
      1. 6.6.1 Watch Variables
      2. 6.6.2 Test Signals
      3. 6.6.3 Pin Usage and Test Connections
    7. 6.7 QepOnClb Example
      1. 6.7.1 Watch Variables
      2. 6.7.2 Header Pin Connections
  8. 7Library Source and Projects
    1. 7.1 Locating the Library Source Code
    2. 7.2 Import and Build the Library Project
    3. 7.3 PTO - PulseGen API
      1. 7.3.1 pto_pulsegen_runPulseGen
      2. 7.3.2 pto_startOperation
      3. 7.3.3 pto_pulsegen_setupPeriph
      4. 7.3.4 pto_pulsegen_reset
    4. 7.4 PTO - QepDiv API
      1. 7.4.1 pto_qepdiv_config
      2. 7.4.2 pto_startOperation
      3. 7.4.3 pto_qepdiv_setupPeriph
      4. 7.4.4 pto_qepdiv_reset
    5. 7.5 PTO - Abs2Qep API
      1. 7.5.1 Abs2Qep API Configuration
      2. 7.5.2 pto_abs2qep_runPulseGen
      3. 7.5.3 pto_abs2qep_setupPeriph
      4. 7.5.4 pto_abs2qep_translatePosition
    6. 7.6 PTO - QepOnClb API
      1. 7.6.1 pto_qeponclb_setupPeriph
      2. 7.6.2 pto_qeponclb_initCLBQEP
      3. 7.6.3 pto_qeponclb_configMaxCounterPos
      4. 7.6.4 pto_qeponclb_enableCLBQEP
      5. 7.6.5 pto_qeponclb_resetCLBQEP
      6. 7.6.6 pto_qeponclb_getCounterVal
      7. 7.6.7 pto_qeponclb_getCLBQEPPos
      8. 7.6.8 pto_qeponclb_clearFIFOptr
  9. 8Using the Reference APIs in Projects
    1. 8.1 Adding PTO Support to a Project
    2. 8.2 Routing To and From the CLB
    3. 8.3 Initialization Steps
      1. 8.3.1 PTO-PulseGen API Initalization
      2. 8.3.2 PTO-QepDiv API Initialization
      3. 8.3.3 PTO-Abs2Qep API Initialization
      4. 8.3.4 PTO-QepOnClb API Initialization
  10. 9References
  11.   Revision History

4.3 Abs2Qep CLB Configuration

After translating the absolute position into QCLK pulses as described in Section 4.2, the C28x loads the PTO parameters into the HLC's FIFO. When it is time to start the PTO, a command via the GPREG bits will signal the HLC to pull the parameters from the FIFO, to load them into the counters, and then to start the PTO. Once started, the CLB generates the PTO-QEP waveform independently.

Once the PTO is complete, the HLC will set a CLB interrupt tag. The C28x can use this to flag to check if the PTO is complete before loading a new configuration.

Figure 4-6 shows PTO-QEP waveforms and their tie to CLB components. In this example, the position sampling period is controlled by an ePWM ISR on the C28x.

Counter 0 match 1 is initialized to a fixed value and is not changed. This match generates the QCLK pulse. This places QCLK toggle at the beginning of the count, reducing the time between the previous PTO halt and the next PTO start.
The time between QCLK pulses is controlled by the COUNTER 0 match 2. This match resets COUNTER 0.
P(n) stands for Absolute Position at sample n.
Figure 4-6 Abs2Qep Example System Waveform

The CLB Tile block diagram is shown in Figure 4-7 and Table 4-3 describes the functionality of each CLB component in detail.

HALT/CLEAR LATCH is controlled directly by HLC during a LOAD event.
PTO_DONE is controlled by the COUNTER 1 incrementing and directly by the HLC during a LOAD event.
Figure 4-7 Abs2Qep CLB Tile Block Diagram
Table 4-3 Abs2Qep CLB Tile 1
Resource Function Notes
Inputs
In0 LOAD control Rising edge:

Loads new PTO configuration (HLC).		 Connected to GPREG bit 0.

Before loading a new configuration, check that the last PTO is complete (INTR tag == 2)
In1 DIRECTION control

1: clockwise (forward)

0: counter-clockwise (backward)

 Connected to GPREG bit 1.
Change only when the last PTO is complete (Intr Tag 2)
In2 Not used Not used
In3 Not used Not used
In4 Not used Not used
In5 Not used Not used
In6 Not used Not used
In7 Not used Not used
Outputs
Out0 Not used Not used
Out1 Not used Not used
Out2 PTO_QEP-I
The index transiton from 0 to 1 indicates the absolute zero position has been crossed.		 The index output signal.
Out3 Not used Not used
Out4 PTO_QEP-A PTO quadrature output A
Out5 PTO_QEP-B PTO quadrature output B
Out6 Not used Not used
Out7 Not used Not used
Logic Resources
LUT0 Not used Not used
LUT1 Not used Not used
LUT2 Not used Not used
FSM0 Generate PTO_QEP-A and PTO-QEP-B Generate 1 edge on each QCLK input. The lead/lag of QEP-A/B is based on the current state and the DIRECTION input signal.
FSM1 Generate HALT/RUN signal Halt the PTO output if either of these conditions is true:
  • The PTO completes. This halt is latched and the PTO will remain halted until the latch is cleared via the HALT/RUN control input
  • The HALT/RUN control input is high.
FSM2 Generate PTO_QEP-I signal Force PTO_QEP-I high and low based on the QEP-I control. Enables the user to configure QEP-I to stay high for more than one QCLK if desired.
CNT0 Generate QCLK (PTO width control) signal Counts up by 1 each CLB clock.
  • match1: fixed value. Generates the QCLK signal near the start of the count. This placement reduces the time between the last PTO halt and the next PTO start.
  • match2: number of CLB clocks between QEP edges. The counter is reset every match2 event.
CNT1 PTO edge-count control Increments by 1 every QCLK event to count the total QEP-A + QEP-B edges sent during a PTO.
  • match1: manipulated by the HLC in order to clear a halt latch condition and start the PTO.
  • match2: number of edges to be sent. Once reached, the PTO_DONE signal is asserted. This latches a halt state and resets the edge count and resets QEP-I control.
CNT2 PTO_QEP-I control Increments by 1 every QCLK event to count the total QEP-A + QEP-B edges sent during a PTO.
  • match1: Edge where PTO_QEP-I will go high
  • match2: Edge where PTO_QEP-I will go low
Note: If PTO-QEP-I should remain low for the whole PTO, then configure match1 and match2 to be a large number to avoid a match. (i.e. 0xFFFFFFFF).
High Level Controller
HLC Event 1: LOAD new PTO configuration.

Responds to a rising edge on the LOAD input from the C28x. This will configure and start a new PTO. For all of the steps, refer to the program description in Section 4.3.3
Event 2: Signal PTO is complete. Responds to the completion of PTO signal by setting Interrupt Tag 2. At this point, it is safe to load a new PTO counter configuration.