SPRAC77E January   2022  – February 2022 TMS320F28379D , TMS320F28379D-Q1 , TMS320F28379S

 

  1.   Trademarks
  2. 1Introduction
  3. 2PTO – PulseGen
    1. 2.1 PulseGen Implementation Overview
    2. 2.2 PulseGen Limitations
    3. 2.3 PulseGen CLB Configuration
    4. 2.4 PulseGen Input and Output Signals
  4. 3PTO – QepDiv
    1. 3.1 QepDiv Implementation Overview
    2. 3.2 QepDiv Limitations
    3. 3.3 QepDiv Divider Settings and Initialization
    4. 3.4 QepDiv CLB Configuration
  5. 4PTO – Abs2Qep
    1. 4.1 Abs2Qep Chip resources
    2. 4.2 Abs2Qep Theory of Operation
      1. 4.2.1 Abs2Qep Translation Equations
      2. 4.2.2 Abs2Qep Translation Example
      3. 4.2.3 Abs2Qep Zero Cross Detection
    3. 4.3 Abs2Qep CLB Configuration
      1. 4.3.1 Abs2Qep QEP-A/B Pulse Train Generation
      2. 4.3.2 Abs2Qep Halt Latch
      3. 4.3.3 Abs2Qep High Level Controller (HLC)
    4. 4.4 Abs2Qep Input and Output Signals
  6. 5PTO – QepOnClb QEP Decoder
    1. 5.1 QepOnClb and eQEP Comparison
    2. 5.2 QepOnClb Chip resources
    3. 5.3 QepOnClb Theory of Operation
    4. 5.4 QepOnClb CLB Resources
      1. 5.4.1 QepOnClb QCLK State Machine
      2. 5.4.2 QepOnClb Direction Decode
      3. 5.4.3 QepOnClb Error Detection
      4. 5.4.4 QepOnClb Simulation Waveforms
  7. 6Example Projects
    1. 6.1 Hardware Requirements
    2. 6.2 Installing Code Composer Studio and C2000WARE-MOTORCONTROL-SDK™
    3. 6.3 Import and Run Example Project
    4. 6.4 PulseGen Example
    5. 6.5 QepDiv Example
    6. 6.6 Abs2Qep Example
      1. 6.6.1 Watch Variables
      2. 6.6.2 Test Signals
      3. 6.6.3 Pin Usage and Test Connections
    7. 6.7 QepOnClb Example
      1. 6.7.1 Watch Variables
      2. 6.7.2 Header Pin Connections
  8. 7Library Source and Projects
    1. 7.1 Locating the Library Source Code
    2. 7.2 Import and Build the Library Project
    3. 7.3 PTO - PulseGen API
      1. 7.3.1 pto_pulsegen_runPulseGen
      2. 7.3.2 pto_startOperation
      3. 7.3.3 pto_pulsegen_setupPeriph
      4. 7.3.4 pto_pulsegen_reset
    4. 7.4 PTO - QepDiv API
      1. 7.4.1 pto_qepdiv_config
      2. 7.4.2 pto_startOperation
      3. 7.4.3 pto_qepdiv_setupPeriph
      4. 7.4.4 pto_qepdiv_reset
    5. 7.5 PTO - Abs2Qep API
      1. 7.5.1 Abs2Qep API Configuration
      2. 7.5.2 pto_abs2qep_runPulseGen
      3. 7.5.3 pto_abs2qep_setupPeriph
      4. 7.5.4 pto_abs2qep_translatePosition
    6. 7.6 PTO - QepOnClb API
      1. 7.6.1 pto_qeponclb_setupPeriph
      2. 7.6.2 pto_qeponclb_initCLBQEP
      3. 7.6.3 pto_qeponclb_configMaxCounterPos
      4. 7.6.4 pto_qeponclb_enableCLBQEP
      5. 7.6.5 pto_qeponclb_resetCLBQEP
      6. 7.6.6 pto_qeponclb_getCounterVal
      7. 7.6.7 pto_qeponclb_getCLBQEPPos
      8. 7.6.8 pto_qeponclb_clearFIFOptr
  9. 8Using the Reference APIs in Projects
    1. 8.1 Adding PTO Support to a Project
    2. 8.2 Routing To and From the CLB
    3. 8.3 Initialization Steps
      1. 8.3.1 PTO-PulseGen API Initalization
      2. 8.3.2 PTO-QepDiv API Initialization
      3. 8.3.3 PTO-Abs2Qep API Initialization
      4. 8.3.4 PTO-QepOnClb API Initialization
  10. 9References
  11.   Revision History

6.6.3 Pin Usage and Test Connections

The output from the PTO is internally routed to GPIOs via the OUTPUTXBARs and by overriding PWM1-B. The code that routes the signals can be found in the functions listed in Table 6-7.

Table 6-7 Abs2Qep Output Signal Routing
Function Location Notes
pto_abs2qep_initCLBXBAR Library Tie Tile out4/5 to OUTPUTXBARs
pto_abs2qep_setupPeriph Library Enable output to override peripheral.
pto_setupGPIO Example application Connect OUTPUTXBARs to GPIO outputs
Table 6-8 F2838xD Abs2Qep Output GPIO Mapping
Abs2Qep Output Test Connections
Abs2Qep Signal Routing From CLB to GPIO GPIO / TMDSHSECDOCK Pin Connect Abs2Qep Output to:
PTO-QEP-A Tile1 out4 to OUTPUTXBAR7 GPIO16 / Pin 67 GPIO20_EQEP1A / Pin 68
PTO-QEP-B Tile1 out5 to OUTPUTXBAR2 GPIO3 / Pin 55 GPIO21_EQEP1B / Pin 70
PTO-QEP-I Tile1 out2, override PWM1-B GPIO1 / Pin 51 GPIO99_EQEP1I / Pin 96
Test signal 1: System PWM ISR / Direction None GPIO32 / Pin 85 Monitor with Oscilloscope
Test signal 2: Internal HALT/RUN Tile1 out0, override PWM1-A GPIO0 / Pin 49 Monitor with Oscilloscope
Table 6-9 F2837xD Abs2Qep Output GPIO Mapping
Abs2Qep Output Test Connections
Abs2Qep Signal Routing From CLB to GPIO GPIO / LAUNCHXL-F28379D Pin Connect Abs2Qep Output to:
PTO-QEP-A Tile1 OUT4 to OUTPUTXBAR7 GPIO16 / J4-33 GPIO20_EQEP1A / J14-1
PTO-QEP-B Tile1 OUT5 to OUTPUTXBAR2 GPIO3 / J4-37 GPIO21_EQEP1B / J14-2
PTO-QEP-I Tile1 OUT2, override PWM1-B GPIO1 / J4-39 GPIO99_EQEP1I / J14-3
Test signal 1: System PWM ISR / Direction None GPIO32 / J1-2 Monitor with Oscilloscope
Test signal 2: Internal HALT/RUN Tile1 OUT0, override PWM1-A GPIO0 / J4-40 Monitor with Oscilloscope
Table 6-10 F280049C Abs2Qep Output GPIO Mapping
Abs2Qep Output Test Connections
Abs2Qep Signal Routing From CLB to GPIO GPIO / LAUNCHXL-F280049C Pin (1) Connect Abs2Qep Output to:
PTO-QEP-A Tile1 OUT4 to OUTPUTXBAR1 GPIO24 / J8-55 GPIO10_EQEP1A / J4-40
PTO-QEP-B Tile1 OUT5 to OUTPUTXBAR2 GPIO3 / J6-75 GPIO11_EQEP1A / J4-39
PTO-QEP-I Tile1 OUT2, override PWM1-B GPIO1 / J6-79 GPIO9_EQEPI / J4-37
Test signal 1: PWM ISR / Direction - GPIO13 / J1-3 Monitor with Oscilloscope.
Test signal 2: HALT/RUN Tile1 OUT0, override PWM1-A GPIO0 / J6-80 Monitor with Oscilloscope.
(1) J8 and J6 are swapped on the silkscreen of RevA F28004x LaunchPad. J8 and J6 Pin numbers in this table refer to the silkscreen on Rev A. To confirm whether this applies to your board, see the "known issues" in the revision section of C2000™ Piccolo™ F28004x Series LaunchPad™ Development Kit.
Table 6-11 F280025C Abs2Qep Output GPIO Mapping
Abs2Qep Output Test Connections
Abs2Qep Signal Routing From CLB to GPIO GPIO / LAUNCHXL-F280025C Pin Connect Abs2Qep Output to:
PTO-QEP-A Tile1 OUT4 to OUTPUTXBAR1 GPIO24 / J5-44/45 GPIO10_EQEP1A / J2-14
PTO-QEP-B Tile1 OUT5 to OUTPUTXBAR2 GPIO3 / J4-37 GPIO11_EQEP1A / J2-15
PTO-QEP-I Tile1 OUT2, override PWM1-B GPIO1 / J4-39 GPIO9_EQEPI / J1-7
Test signal 1: PWM ISR / Direction - GPIO13 / J8-79 Monitor with Oscilloscope.
Test signal 2: HALT/RUN Tile1 OUT0, override PWM1-A GPIO0 / J4-40 Monitor with Oscilloscope.
Table 6-12 F280039C Abs2Qep Output GPIO Mapping
Abs2Qep Output Test Connections
Abs2Qep Signal Routing From CLB to GPIO GPIO / LAUNCHXL-F280039C Pin Connect Abs2Qep Output to:
PTO-QEP-A Tile1 OUT4 to OUTPUTXBAR1 GPIO24 / J1-8 GPIO10_EQEP1A / J4-36
PTO-QEP-B Tile1 OUT5 to OUTPUTXBAR2 GPIO3 / J4-37 GPIO11_EQEP1A / J4-35
PTO-QEP-I Tile1 OUT2, override PWM1-B GPIO1 / J4-39 GPIO9_EQEPI / J1-7
Test signal 1: PWM ISR / Direction - GPIO13 / J8-79 Monitor with Oscilloscope.
Test signal 2: HALT/RUN Tile1 OUT0, override PWM1-A GPIO0 / J4-40 Monitor with Oscilloscope.