SPRAC77E January   2022  – February 2022 TMS320F28379D , TMS320F28379D-Q1 , TMS320F28379S

 

  1.   Trademarks
  2. 1Introduction
  3. 2PTO – PulseGen
    1. 2.1 PulseGen Implementation Overview
    2. 2.2 PulseGen Limitations
    3. 2.3 PulseGen CLB Configuration
    4. 2.4 PulseGen Input and Output Signals
  4. 3PTO – QepDiv
    1. 3.1 QepDiv Implementation Overview
    2. 3.2 QepDiv Limitations
    3. 3.3 QepDiv Divider Settings and Initialization
    4. 3.4 QepDiv CLB Configuration
  5. 4PTO – Abs2Qep
    1. 4.1 Abs2Qep Chip resources
    2. 4.2 Abs2Qep Theory of Operation
      1. 4.2.1 Abs2Qep Translation Equations
      2. 4.2.2 Abs2Qep Translation Example
      3. 4.2.3 Abs2Qep Zero Cross Detection
    3. 4.3 Abs2Qep CLB Configuration
      1. 4.3.1 Abs2Qep QEP-A/B Pulse Train Generation
      2. 4.3.2 Abs2Qep Halt Latch
      3. 4.3.3 Abs2Qep High Level Controller (HLC)
    4. 4.4 Abs2Qep Input and Output Signals
  6. 5PTO – QepOnClb QEP Decoder
    1. 5.1 QepOnClb and eQEP Comparison
    2. 5.2 QepOnClb Chip resources
    3. 5.3 QepOnClb Theory of Operation
    4. 5.4 QepOnClb CLB Resources
      1. 5.4.1 QepOnClb QCLK State Machine
      2. 5.4.2 QepOnClb Direction Decode
      3. 5.4.3 QepOnClb Error Detection
      4. 5.4.4 QepOnClb Simulation Waveforms
  7. 6Example Projects
    1. 6.1 Hardware Requirements
    2. 6.2 Installing Code Composer Studio and C2000WARE-MOTORCONTROL-SDK™
    3. 6.3 Import and Run Example Project
    4. 6.4 PulseGen Example
    5. 6.5 QepDiv Example
    6. 6.6 Abs2Qep Example
      1. 6.6.1 Watch Variables
      2. 6.6.2 Test Signals
      3. 6.6.3 Pin Usage and Test Connections
    7. 6.7 QepOnClb Example
      1. 6.7.1 Watch Variables
      2. 6.7.2 Header Pin Connections
  8. 7Library Source and Projects
    1. 7.1 Locating the Library Source Code
    2. 7.2 Import and Build the Library Project
    3. 7.3 PTO - PulseGen API
      1. 7.3.1 pto_pulsegen_runPulseGen
      2. 7.3.2 pto_startOperation
      3. 7.3.3 pto_pulsegen_setupPeriph
      4. 7.3.4 pto_pulsegen_reset
    4. 7.4 PTO - QepDiv API
      1. 7.4.1 pto_qepdiv_config
      2. 7.4.2 pto_startOperation
      3. 7.4.3 pto_qepdiv_setupPeriph
      4. 7.4.4 pto_qepdiv_reset
    5. 7.5 PTO - Abs2Qep API
      1. 7.5.1 Abs2Qep API Configuration
      2. 7.5.2 pto_abs2qep_runPulseGen
      3. 7.5.3 pto_abs2qep_setupPeriph
      4. 7.5.4 pto_abs2qep_translatePosition
    6. 7.6 PTO - QepOnClb API
      1. 7.6.1 pto_qeponclb_setupPeriph
      2. 7.6.2 pto_qeponclb_initCLBQEP
      3. 7.6.3 pto_qeponclb_configMaxCounterPos
      4. 7.6.4 pto_qeponclb_enableCLBQEP
      5. 7.6.5 pto_qeponclb_resetCLBQEP
      6. 7.6.6 pto_qeponclb_getCounterVal
      7. 7.6.7 pto_qeponclb_getCLBQEPPos
      8. 7.6.8 pto_qeponclb_clearFIFOptr
  9. 8Using the Reference APIs in Projects
    1. 8.1 Adding PTO Support to a Project
    2. 8.2 Routing To and From the CLB
    3. 8.3 Initialization Steps
      1. 8.3.1 PTO-PulseGen API Initalization
      2. 8.3.2 PTO-QepDiv API Initialization
      3. 8.3.3 PTO-Abs2Qep API Initialization
      4. 8.3.4 PTO-QepOnClb API Initialization
  10. 9References
  11.   Revision History

6.7.2 Header Pin Connections

In this example, EPWMs are generated by the device and are meant to simulate test QEP signals. These EPWM signals need to be externally routed to both the CLB INPUTXBARs and the on-board eQEP peripheral. The following two tables describe the necessary pin connections that need to be made depending on the device being used.

Note:

The EPWM signals serve as test inputs to showcase the functionality of the QepOnClb example. If desired, users can instead route external QEP-A and QEP-B signals to the INPUTXBARs and eQEP peripheral.

The CLB-based QEP decoder module is configured to accept three inputs corresponding to QEP-A, QEP-B, and QEP-I. The QEP-A signal should be routed into INPUTXBAR2, the QEP-B signal should be routed into INPUTXBAR1, and the QEP-I signal should be routed into INPUTXBAR3.

Table 6-13 lists the connections that need to be made to route the EPWM signals to the CLB X-BARs.

Table 6-13 QepOnClb EPWM to CLB INPUTXBAR Connections
BoardEPWMA to

INPUTXBAR2 (QEP-A)

EPWMB to

INPUTXBAR1 (QEP-B)

GPIO to INPUTXBAR3 (QEP-I)

LAUNCHXL-F280025C

GPIO0 (J4-40) to GPIO8 (J2-12)

GPIO1 (J4-39) to GPIO9 (J1-7)

GPIO2 (J4-38) to GPIO27 (J2-11)

LAUNCHXL-F280039C

GPIO0 (J4-40) to GPIO8 (J2-15)

GPIO1 (J4-39) to GPIO9 (J1-7)

GPIO2 (J4-38) to GPIO27 (J6-59)

LAUNCHXL-F280049C

GPIO10 (J4-40) to GPIO39 (J2-13)

GPIO11 (J4-39) to GPIO40 (J1-4)

GPIO8 (J4-38) to GPIO27 (J6-59)

LAUNCHXL-F28379D

GPIO0 (J4-40) to GPIO18 (J1-4)

GPIO1 (J4-39) to GPIO40 (J5-50)

GPIO2 (J4-38) to GPIO27 (J6-52)

TMDSCNCD28388D

GPIO0 (Pin 49) to GPIO18 (Pin 71)

GPIO1 (Pin 51) to GPIO40 (Pin 89)

GPIO2 (Pin 53) to GPIO27 (Pin 81)

The EPWM signals are routed to the eQEP peripheral for loopback testing. This is done in order to provide a comparison with the CLB-based QEP module.

Table 6-13 lists the connections that need to be made to route the EPWM signals to the eQEP peripheral.

Table 6-14 QepOnClb EPWM to eQEP Connections
BoardEPWMA to eQEP-AEPWMB to eQEP-B

GPIO to eQEP-I

LAUNCHXL-F280025C

GPIO0 (J4-40) to GPIO25 (J4-31)

GPIO1 (J4-39) to GPIO29 (J1-4/5)

GPIO2 (J4-38) to GPIO23 (J2-13)

LAUNCHXL-F280039C

GPIO0 (J4-40) to GPIO25 (J6-51)

GPIO1 (J4-39) to GPIO29 (J1-4/5)

GPIO2 (J4-38) to GPIO23 (J2-11)

LAUNCHXL-F280049CGPIO10 (J4-40) to GPIO35 (J1-10)GPIO11 (J4-39) to GPIO37 (J1-9)GPIO8 (J4-38) to GPIO59 (J2-11)
LAUNCHXL-F28379DGPIO0

(J4-40) to GPIO20 (QEP1A)

GPIO1 (J4-39) to GPIO21 (QEP1B)

GPIO2 (J4-38) to GPIO23 (QEP1I)

TMDSCNCD28388DGPIO0 (Pin 49) to

GPIO20 (Pin 68)

GPIO1 (Pin 51) to

GPIO21 (Pin 70)

GPIO2 (Pin 53) to

GPIO23 (Pin 74)