SPRAC77E January   2022  – February 2022 TMS320F28379D , TMS320F28379D-Q1 , TMS320F28379S

 

  1.   Trademarks
  2. 1Introduction
  3. 2PTO – PulseGen
    1. 2.1 PulseGen Implementation Overview
    2. 2.2 PulseGen Limitations
    3. 2.3 PulseGen CLB Configuration
    4. 2.4 PulseGen Input and Output Signals
  4. 3PTO – QepDiv
    1. 3.1 QepDiv Implementation Overview
    2. 3.2 QepDiv Limitations
    3. 3.3 QepDiv Divider Settings and Initialization
    4. 3.4 QepDiv CLB Configuration
  5. 4PTO – Abs2Qep
    1. 4.1 Abs2Qep Chip resources
    2. 4.2 Abs2Qep Theory of Operation
      1. 4.2.1 Abs2Qep Translation Equations
      2. 4.2.2 Abs2Qep Translation Example
      3. 4.2.3 Abs2Qep Zero Cross Detection
    3. 4.3 Abs2Qep CLB Configuration
      1. 4.3.1 Abs2Qep QEP-A/B Pulse Train Generation
      2. 4.3.2 Abs2Qep Halt Latch
      3. 4.3.3 Abs2Qep High Level Controller (HLC)
    4. 4.4 Abs2Qep Input and Output Signals
  6. 5PTO – QepOnClb QEP Decoder
    1. 5.1 QepOnClb and eQEP Comparison
    2. 5.2 QepOnClb Chip resources
    3. 5.3 QepOnClb Theory of Operation
    4. 5.4 QepOnClb CLB Resources
      1. 5.4.1 QepOnClb QCLK State Machine
      2. 5.4.2 QepOnClb Direction Decode
      3. 5.4.3 QepOnClb Error Detection
      4. 5.4.4 QepOnClb Simulation Waveforms
  7. 6Example Projects
    1. 6.1 Hardware Requirements
    2. 6.2 Installing Code Composer Studio and C2000WARE-MOTORCONTROL-SDK™
    3. 6.3 Import and Run Example Project
    4. 6.4 PulseGen Example
    5. 6.5 QepDiv Example
    6. 6.6 Abs2Qep Example
      1. 6.6.1 Watch Variables
      2. 6.6.2 Test Signals
      3. 6.6.3 Pin Usage and Test Connections
    7. 6.7 QepOnClb Example
      1. 6.7.1 Watch Variables
      2. 6.7.2 Header Pin Connections
  8. 7Library Source and Projects
    1. 7.1 Locating the Library Source Code
    2. 7.2 Import and Build the Library Project
    3. 7.3 PTO - PulseGen API
      1. 7.3.1 pto_pulsegen_runPulseGen
      2. 7.3.2 pto_startOperation
      3. 7.3.3 pto_pulsegen_setupPeriph
      4. 7.3.4 pto_pulsegen_reset
    4. 7.4 PTO - QepDiv API
      1. 7.4.1 pto_qepdiv_config
      2. 7.4.2 pto_startOperation
      3. 7.4.3 pto_qepdiv_setupPeriph
      4. 7.4.4 pto_qepdiv_reset
    5. 7.5 PTO - Abs2Qep API
      1. 7.5.1 Abs2Qep API Configuration
      2. 7.5.2 pto_abs2qep_runPulseGen
      3. 7.5.3 pto_abs2qep_setupPeriph
      4. 7.5.4 pto_abs2qep_translatePosition
    6. 7.6 PTO - QepOnClb API
      1. 7.6.1 pto_qeponclb_setupPeriph
      2. 7.6.2 pto_qeponclb_initCLBQEP
      3. 7.6.3 pto_qeponclb_configMaxCounterPos
      4. 7.6.4 pto_qeponclb_enableCLBQEP
      5. 7.6.5 pto_qeponclb_resetCLBQEP
      6. 7.6.6 pto_qeponclb_getCounterVal
      7. 7.6.7 pto_qeponclb_getCLBQEPPos
      8. 7.6.8 pto_qeponclb_clearFIFOptr
  9. 8Using the Reference APIs in Projects
    1. 8.1 Adding PTO Support to a Project
    2. 8.2 Routing To and From the CLB
    3. 8.3 Initialization Steps
      1. 8.3.1 PTO-PulseGen API Initalization
      2. 8.3.2 PTO-QepDiv API Initialization
      3. 8.3.3 PTO-Abs2Qep API Initialization
      4. 8.3.4 PTO-QepOnClb API Initialization
  10. 9References
  11.   Revision History

4.3.2 Abs2Qep Halt Latch

The HALT_LATCH and RUN/HALT output is implemented using a finite state machine. The output signal is connected to the mode0 input of the counter which generates QCLK. The RUN/HALT output depends only on the current state of the latch and the HALT signal from the CPU. If the HALT signal is low, and the latch is not set, then QCLK will be generated (COUNTER mode0 = out = 1). In all other cases QCLK will not be generated (COUNTER mode0 = out = 0). This is expressed as out = !(s0 | e1).

Table 4-6 RUN/HALT Output
s0
(LATCH)		 e1
(HALT/CLEAR LATCH)		 out = !(s0|e1) QCLK Generation
0 0 1 Run
0 1 0 Halt
1 0 0 Halt
1 1 0 Halt

HALT_LATCH is set on the rising edge of PTO_DONE. It will remain set until cleared by a a rising edge on the HALT/CLEAR_LATCH signal from the CPU.

Table 4-7 HALT_LATCH Karnaugh Map
PTO_DONE, CLEAR_LATCH (e0, e1)
00 01 11 10
s0
(LATCH)		 0 0 0 0 1 (2)
1 1 (1) 0 0 1 (1),(2)
(1) s0_1 = s0 & !e1
(2) s0_2 = e0 & !e1

The Halt Latch SystemC simulation is shown in Figure 4-10.

GUID-20210319-CA0I-LS0V-CNFR-HTSFR2XBB70T-low.png Figure 4-10 Simulation of Halt Latch